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| INTEGRATED CIRCUITS DATA SHEET SAA7373 Digital servo processor and Compact Disc decoder (CD7) Product specification File under Integrated Circuits, IC01 1998 Jul 06 Philips Semiconductors Product specification Digital servo processor and Compact Disc decoder (CD7) CONTENTS 1 2 3 4 5 6 7 7.1 7.1.1 7.1.2 7.1.3 7.1.4 7.2 7.3 7.4 7.4.1 7.4.2 7.5 7.5.1 7.5.2 7.5.3 7.6 7.6.1 7.6.2 7.7 7.7.1 7.7.2 7.7.3 7.7.4 7.7.5 7.8 7.9 7.9.1 7.10 7.11 7.12 7.13 7.13.1 7.13.3 7.13.4 FEATURES GENERAL DESCRIPTION QUICK REFERENCE DATA ORDERING INFORMATION BLOCK DIAGRAM PINNING FUNCTIONAL DESCRIPTION Decoder part Principle operational modes of the decoder Decoding speed and crystal frequency Lock-to-disc mode Standby modes Crystal oscillator Data slicer and clock regenerator Demodulator Frame sync protection EFM demodulation Subcode data processing Q-channel processing EIAJ 3 and 4-wire subcode (CD graphics) interface V4 subcode interface FIFO error corrector Flags output (CFLG) C2FAIL Audio functions De-emphasis and phase linearity Digital oversampling filter Concealment Mute, full-speed, attenuation and fade Peak detector DAC interface EBU interface Format KILL circuit Audio features off The VIA interface Spindle motor control Motor output modes Loop characteristics FIFO overflow 7.14 7.14.1 7.14.2 7.14.3 7.14.4 7.14.5 7.14.6 7.14.7 7.14.8 7.14.9 7.15 7.15.1 7.15.2 7.15.3 7.15.4 7.15.5 8 9 10 11 12 13 14 15 15.1 15.2 15.3 15.4 16 17 18 SAA7373 Servo part Diode signal processing Signal conditioning Focus servo system Radial servo system Off-track counting Defect detection Off-track detection High level features Driver interface Microcontroller interface Microprocessor interface (4-wire bus mode) Microcontroller interface (I2C-bus mode) Summary of functions controlled by registers 0 to F Summary of servo commands Summary of servo command parameters LIMITING VALUES OPERATING CHARACTERISTICS OPERATING CHARACTERISTICS (SUBCODE INTERFACE TIMING) OPERATING CHARACTERISTICS (I2S-BUS TIMING) OPERATING CHARACTERISTICS (MICROCONTROLLER INTERFACE TIMING) APPLICATION INFORMATION PACKAGE OUTLINE SOLDERING Introduction Reflow soldering Wave soldering Repairing soldered joints DEFINITIONS LIFE SUPPORT APPLICATIONS PURCHASE OF PHILIPS I2C COMPONENTS 1998 Jul 06 2 Philips Semiconductors Product specification Digital servo processor and Compact Disc decoder (CD7) 1 FEATURES SAA7373 * CD ROM mode * Single and double-speed modes * Lock-to-disc mode * Full error correction strategy, t = 2 and e = 4 * Full CD graphics interface * All standard decoder functions implemented digitally on chip * FIFO overflow concealment for rotational shock resistance * Digital audio interface (EBU), audio and data * 2 and 4 times oversampling integrated digital filter, including fs mode * Audio data peak level detection * Kill interface for DAC deactivation during digital silence * All TDA1301 (DSIC2) digital servo functions, plus extra high-level functions * Low focus noise * Improved playability on ABEX TCD-721R, TCD-725 and TCD-714 discs * Automatic closed loop gain control available for focus and radial loops * Pulsed sledge support 3 QUICK REFERENCE DATA SYMBOL VDD IDD fxtal Tamb Tstg 4 PARAMETER supply voltage supply current crystal frequency operating ambient temperature storage temperature n = 1 mode CONDITIONS 3.4 - 8 -40 -55 MIN. TYP. 5.0 49 8.4672 - - - 35 +85 +125 MAX. 5.5 V mA MHz C C UNIT * Microcontroller loading LOW * High-level servo control option * High-level mechanism monitor * Communication may be via TDA1301/SAA7345 compatible bus or I2C-bus * On-chip clock multiplier allows the use of 8.4672 MHz crystal. 2 GENERAL DESCRIPTION The SAA7373 is a single chip combining the functions of a CD decoder IC and digital servo IC. The decoder part is based on the SAA7345 (CD6) with an improved error correction strategy. The servo part is based on the TDA1301T (DSIC2) with improvements incorporated, extra features have also been added. Supply of this Compact Disc IC does not convey an implied license under any patent right to use this IC in any Compact Disc application. ORDERING INFORMATION TYPE NUMBER PACKAGE NAME QFP64 DESCRIPTION plastic quad flat package; 64 leads (lead length 1.6 mm); body 14 x 14 x 2.7 mm VERSION SOT393-1 SAA7373GP 1998 Jul 06 3 Philips Semiconductors Product specification Digital servo processor and Compact Disc decoder (CD7) 5 BLOCK DIAGRAM VSSA2 VDDA1 VSSD1 VSSD3 VDDD1(P) VDDD3(C) D4 IrefT VSSA1 VSSA3 VDDA2 VSSD2 VSSD4 VDDD2(P) 7 10 1 12 16 2 19 32 39 49 56 30 47 59 SAA7373 handbook, full pagewidth VRL D1 D2 6 3 4 D3 5 R1 R2 8 9 ADC PREPROCESSING CONTROL FUNCTION OUTPUT STAGES 26 27 28 RA FO SL VRH 11 Vref GENERATOR CONTROL PART 64 SCL SDA RAB SILD 52 51 53 54 MICROCONTROLLER INTERFACE LDON SAA7373 DIGITAL PLL FRONT END 33 MOTOR CONTROL 34 HFIN HFREF ISLICE Iref 15 17 14 18 EFM DEMODULATOR TEST ERROR CORRECTOR FLAGS SRAM 60 AUDIO PROCESSOR RAM ADDRESSER EBU INTERFACE 31 61 CFLG MOTO1 MOTO2 TEST1 TEST2 TEST3 20 23 29 SELPLL CRIN CROUT CL16 CL11 CL4 13 21 22 24 25 50 TIMING C2FAIL DOBM SBSY SFSY SUB RCK 35 36 38 37 SUBCODE PROCESSOR PEAK DETECT 48 DECODER MICROCONTROLLER INTERFACE 46 SERIAL DATA INTERFACE VERSATILE PINS INTERFACE KILL 45 44 SCLK WCLK DATA EF STATUS 58 RESET 57 62 63 42 41 40 43 MGR321 V1 V2 V3 V4 V5 KILL Fig.1 Block diagram. 1998 Jul 06 4 Philips Semiconductors Product specification Digital servo processor and Compact Disc decoder (CD7) 6 PINNING SYMBOL VSSA1 VDDA1 D1 D2 D3 VRL D4 R1 R2 IrefT VRH VSSA2 SELPLL ISLICE HFIN VSSA3 HFREF Iref VDDA2 TEST1 CRIN CROUT TEST2 CL16 CL11 RA FO SL TEST3 VDDD1(P) DOBM VSSD1 MOTO1 MOTO2 SBSY SFSY RCK SUB VSSD2 V5 1998 Jul 06 PIN 1(1) 2(1) 3 4 5 6 7 8 9 10 11 12(1) 13 14 15 16(1) 17 18 19(1) 20 21 22 23 24 25 26 27 28 29 30(1) 31 32(1) 33 34 35 36 37 38 39(1) 40 analog ground 1 analog supply voltage 1 unipolar current input (central diode signal input) unipolar current input (central diode signal input) unipolar current input (central diode signal input) reference voltage input for ADC unipolar current input (central diode signal input) unipolar current input (satellite diode signal input) unipolar current input (satellite diode signal input) current reference output for ADC calibration reference voltage output from ADC analog ground 2 selects whether internal clock multiplier PLL is used current feedback output from data slicer comparator signal input analog ground 3 comparator common mode input reference current output pin (nominally 0.5VDD) analog supply voltage 2 test control input 1; this pin should be tied LOW crystal/resonator input crystal/resonator output test control input 2; this pin should be tied LOW 16.9344 MHz system clock output 11.2896 or 5.6448 MHz clock output (3-state) radial actuator output focus actuator output sledge control output test control input 3; this pin should be tied LOW digital supply voltage 1 for periphery bi-phase mark output (externally buffered; 3-state) digital ground 1 motor output 1; versatile (3-state) motor output 2; versatile (3-state) subcode block sync output (3-state) subcode frame sync output (3-state) subcode clock input P-to-W subcode output bits (3-state) digital ground 2 versatile output pin 5 5 DESCRIPTION SAA7373 Philips Semiconductors Product specification Digital servo processor and Compact Disc decoder (CD7) SYMBOL V4 V3 KILL EF DATA WCLK VDDD2(P) SCLK VSSD3 CL4 SDA SCL RAB SILD n.c. VSSD4 RESET STATUS VDDD3(C) C2FAIL CFLG V1 V2 LDON Note 1. All supply pins must be connected to the same external power supply voltage. PIN 41 42 43 44 45 46 47(1) 48 49(1) 50 51 52 53 54 55 56(1) 57 58 59(1) 60 61 62 63 64 versatile output pin 4 versatile output pin 3 (open-drain) kill output (programmable; open-drain) DESCRIPTION SAA7373 C2 error flag; output only defined in CD ROM modes and 1fs modes (3-state) serial data output (3-state) word clock output (3-state) digital supply voltage 2 for periphery serial bit clock output (3-state) digital ground 3 4.2336 MHz microcontroller clock output microcontroller interface data I/O line (open-drain output) microcontroller interface clock line input microcontroller interface R/W and load control line input (4-wire bus mode) microcontroller interface R/W and load control line input (4-wire-bus mode) not connected digital ground 4 power-on reset input (active LOW) servo interrupt request line/decoder status register output (open-drain) digital supply voltage 3 for core indication of correction failure output (open-drain) correction flag output (open-drain) versatile input pin 1 versatile input pin 2 laser drive on output (open-drain) 1998 Jul 06 6 Philips Semiconductors Product specification Digital servo processor and Compact Disc decoder (CD7) SAA7373 59 V DDD3(C) 60 C2FAIL 57 RESET 56 V SSD4 VSSA1 VDDA1 D1 D2 D3 VRL D4 R1 R2 1 2 3 4 5 6 7 8 49 V SSD3 48 SCLK 47 V DDD2(P) 46 WCLK 45 DATA 44 EF 43 KILL 42 V3 41 V4 40 V5 39 V SSD2 38 SUB 37 RCK 36 SFSY 35 SBSY 34 MOTO2 33 MOTO1 VSSD1 32 MGR322 handbook, full pagewidth 58 STATUS 64 LDON 61 CFLG 54 SILD 53 RAB 51 SDA VDDD1(P) 30 52 SCL SAA7373 9 IrefT 10 VRH 11 VSSA2 12 SELPLL 13 ISLICE 14 HFIN 15 VSSA3 16 HFREF 17 Iref 18 VDDA2 19 TEST1 20 CRIN 21 CROUT 22 TEST2 23 CL16 24 CL11 25 RA 26 FO 27 SL 28 TEST3 29 DOBM 31 Fig.2 Pin configuration. 1998 Jul 06 7 50 CL4 55 n.c. 63 V2 62 V1 Philips Semiconductors Product specification Digital servo processor and Compact Disc decoder (CD7) 7 7.1 7.1.1 FUNCTIONAL DESCRIPTION Decoder part PRINCIPLE OPERATIONAL MODES OF THE DECODER SAA7373 there is a limit on the maximum variation in disc speed that the SAA7373 will follow. Disc speeds must always be within 25 to 100% range of their nominal value. The lock-to-disc mode is enabled/disabled by register E. 7.1.4 STANDBY MODES The decoding part can operate at different disc speeds, single-speed (n = 1) and double-speed (n = 2). The factor `n' is called the overspeed factor. A simplified data flow through the decoder part is illustrated in Fig.6. 7.1.2 DECODING SPEED AND CRYSTAL FREQUENCY The SAA7373 may be placed in two standby modes selected by register B (it should be noted that the device core is still active) Standby 1: "CD-STOP" mode. Most I/O functions are switched off. Standby 2: "CD-PAUSE" mode. Audio output features are switched off, but the motor loop, the motor output and the subcode interfaces remain active. This is also called a "Hot Pause". In the standby modes the various pins will have the following values; MOTO1 and MOTO2: put in high-impedance, PWM mode (standby 1 and reset, operating in standby 2). Put in high-impedance, PDM mode (standby 1 and reset, operating in standby 2). SCL, SDA, SILD and RAB: no interaction. Normal operation continues. SCLK, WCLK, DATA, EF, CL11 and DOBM: 3-state in both standby modes. Normal operation continues after reset. CRIN, CROUT, CL16 and CL4: no interaction. Normal operation continues. V1, V2, V3, V4, V5, CFLG and C2FAIL: no interaction. Normal operation continues. The SAA7373 is a multi-speed decoding device, with an internal phase-locked loop (PLL) clock multiplier. Depending on the crystal frequency used and the internal clock settings (selectable via register B), two playback speeds shown in Table 1 are possible, where `n' is the overspeed factor. An internal clock multiplier is present, controlled by SELPLL, and should only be used if an 8.4672 MHz crystal, ceramic resonator or external clock is present. 7.1.3 LOCK-TO-DISC MODE For high speed CD-ROM applications, the SAA7373 has a special mode, the lock-to-disc mode. This allows Constant Angular Velocity (CAV) disc playback with varying input data rates from the inside-to-outside of the disc. In the lock-to-disc mode, the FIFO is blocked and the decoder will adjust its output data rate to the disc speed. Hence, the frequency of the I2S-bus clocks (WCLK and SCLK) are dependent on the disc speed. In the lock-to-disc mode Table 1 Playback speeds CRYSTAL FREQUENCY (MHz) REGISTER B 00xx 00xx 01xx 10xx 10xx 11xx Notes SELPLL 33.8688 0 1 0 0 1 0 n=1 - - n=2 - - 16.9344 - - n=1 - - n = 2(2) 8.4672 - n=1 - - n=2 - CL11 FREQUENCY (MHz)(1) 11.2896 11.2896 5.6448 11.2896 11.2896 5.6448 1. The CL11 output is always a 5.6448 MHz clock if a 16.9344 MHz external clock is used and SELPLL = 0. 2. Data capture performance is not optimized for these options. 1998 Jul 06 8 Philips Semiconductors Product specification Digital servo processor and Compact Disc decoder (CD7) 7.2 Crystal oscillator 7.3 SAA7373 Data slicer and clock regenerator The crystal oscillator is a conventional 2 pin design operating between 8 and 35 MHz. This oscillator is capable of operating with ceramic resonators also with both fundamental and third overtone crystals. External components should be used to suppress the fundamental output of the third overtone crystals as shown in Figs 3 and 4. Typical oscillation frequencies required are 8.4672, 16.9344 or 33.8688 MHz depending on the internal clock settings used and whether or not the clock multiplier is enabled. The SAA7373 has an integrated slice level comparator which can be clocked by the crystal frequency clock, or 8 times the crystal frequency clock (if SELPLL is set HIGH while using an 8.4672 MHz crystal, and register 4 is set to 0xxx). The slice level is controlled by an internal current source applied to an external capacitor under the control of the Digital Phase-Locked Loop (DPLL). Regeneration of the bit clock is achieved with an internal fully digital PLL. No external components are required and the bit clock is not output. The PLL has two registers (8 and 9) for selecting bandwidth and equalization. For certain applications an off-track input is necessary. This is internally connected from the servo part (its polarity can be changed by the foc_parm1 parameter), but may be input via the V1 pin if selected by register C. If this flag is HIGH, the SAA7373 will assume that its servo part is following on the wrong track and will flag all incoming HF data as incorrect. SAA7373 OSCILLATOR CROUT 330 8.4672 MHz CRIN 100 k 22 pF MGR323 22 pF Fig.3 8.4672 MHz fundamental configuration. SAA7373 OSCILLATOR CROUT 330 33.8688 MHz CRIN 3.3 H 100 k 10 pF 10 pF 1 nF MGR324 Fig.4 33.8688 MHz overtone configuration. 1998 Jul 06 9 Philips Semiconductors Product specification Digital servo processor and Compact Disc decoder (CD7) SAA7373 crystal clock 2.2 k 2.2 nF 47 pF HFREF 22 k 22 nF VSSA 100 nF VSSA ISLICE 100 A Iref 1/2VDD 100 A VSS VDD DPLL HFIN D Q HF input MGA368 - 1 Fig.5 Data slicer showing typical application components (for n = 1). 7.4 7.4.1 Demodulator FRAME SYNC PROTECTION The PLL lock signal can be accessed via the SDA or STATUS pins selected by register 2 and 7. Also incorporated in the demodulator is a Run Length 2 (RL2) correction circuit. Every symbol detected as RL2 will be pushed back to RL3. To do this, the phase error of both edges of the RL2 symbol are compared and the correction is executed at the side with the highest error probability. 7.4.2 EFM DEMODULATION A double timing system is used to protect the demodulator from erroneous sync patterns in the serial data. The master counter is only reset if: * A sync coincidence detected; sync pattern occurs 588 1 EFM clocks after the previous sync pattern * A new sync pattern is detected within 6 EFM clocks of its expected position. The sync coincidence signal is also used to generate the PLL lock signal, which is active HIGH after 1 sync coincidence found, and reset LOW if during 61 consecutive frames no sync coincidence is found. The 14-bit EFM data and subcode words are decoded into 8-bit symbols. 1998 Jul 06 10 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... 1998 Jul 06 1 0 V4 SBSY SFSY SUB MICROCONTROLLER INTERFACE 0 : reg D = xx01 V4 SUBCODE INTERFACE reg F SUBCODE PROCESSOR output from data slicer DIGITAL PLL AND DEMODULATOR 1 : reg A = xx0x 0 : reg A = xx1x 1 Philips Semiconductors CD GRAPHICS INTERFACE handbook, full pagewidth SDA EBU INTERFACE DOBM reg A Digital servo processor and Compact Disc decoder (CD7) 11 FIFO ERROR CORRECTOR FADE/MUTE/ INTERPOLATE 0 1 : reg 3 = xx10 (1fs mode) 0 : reg 3 xx10 1 : no pre-emphasis detected OR reg D = 01xx (de-emphasis signal at V5) 0 : pre-emphasis detected AND reg D 01xx 1 DIGITAL FILTER 0 PHASE COMPENSATION 1 0 1 0 1 0 I2S-BUS INTERFACE SCLK WCLK DATA EF reg 3 KILL KILL V3 DE-EMPHASIS FILTER reg 3 1 : reg 3 101x 0 : reg 3 = 101x (CD-ROM modes) reg C MBG418 Product specification SAA7373 Fig.6 Simplified data flow of decoder functions. Philips Semiconductors Product specification Digital servo processor and Compact Disc decoder (CD7) 7.5 7.5.1 Subcode data processing Q-CHANNEL PROCESSING 7.5.3 V4 SUBCODE INTERFACE SAA7373 The 96-bit Q-channel word is accumulated in an internal buffer. The last 16 bits are used internally to perform a Cyclic Redundancy Check (CRC). If the data is good, the SUBQREADY-I signal will go LOW. SUBQREADY-I can be read via the SDA or STATUS pins, selected via register 2. Good Q-channel data may be read from SDA. 7.5.2 EIAJ 3 AND 4-WIRE SUBCODE (CD GRAPHICS) INTERFACES Data of subcode channels, Q-to-W, may be read via pin V4 if selected via register D. The format is similar to RS232 and is illustrated in Fig.8. The subcode sync word is formed by a pause of (200/n) s minimum. Each subcode byte starts with a logic 1 followed by 7 bits (Q-to-W). The gap between bytes is variable between (11.3/n) s and (90/n) s. The subcode data is also available in the EBU output (DOBM) in a similar format. Data from all the subcode channels (P-to-W) may be read via the subcode interface, which conforms to EIAJ CP-2401. The interface is enabled and configured as either a 3-wire or 4-wire interface via register F. The subcode interface output formats are illustrated in Fig.7, where the RCK signal is supplied by another device such as a CD graphics decoder. handbook, full pagewidth SF0 SF1 SF2 SF3 SF97 SF0 SF1 SBSY SFSY RCK P-W SUB EIAJ 4-wire subcode interface P-W P-W SF0 SFSY RCK SF1 SF2 SF3 SF97 SF0 SF1 P-W SUB P-W P-W EIAJ 3-wire subcode interface SFSY RCK P SUB Q R S T U V W MBG410 Fig.7 EIAJ subcode (CD graphics) interface format. 1998 Jul 06 12 Philips Semiconductors Product specification Digital servo processor and Compact Disc decoder (CD7) SAA7373 200/n s min W96 1 11.3/n s Q R S T U V W 11.3/n s min 90/n s max 1 Q MBG401 n = disc speed Fig.8 Subcode format and timing on pin V4. 7.6 FIFO and error corrector 7.6.1 FLAGS OUTPUT (CFLG) The SAA7373 has a 8 frame FIFO. The error corrector is a t = 2, e = 4 type, with error corrections on both C1 (32 symbol) and C2 (28 symbol) frames. Four symbols are used from each frame as parity symbols. This error corrector can correct up to two errors on the C1 level and up to four errors on the C2 level. The error corrector also contains a flag processor. Flags are assigned to symbols when the error corrector cannot ascertain if the symbols are definitely good. C1 generates output flags which are read after (de-interleaving) by C2, to help in the generation of C2 output flags. The C2 output flags are used by the interpolator for concealment of uncorrectable errors. They are also output via the EBU signal (DOBM) and the EF output with I2S-bus for CD ROM applications. The flags output pin CFLG (open-drain) shows the status of the error corrector and interpolator and is updated every frame (7.35 x n kHz). In the SAA7373 chip a 1-bit flag is present on the CFLG pin as illustrated in Fig.9. This signal shows the status of the error corrector and interpolator. The first flag bit, F1, is the absolute time sync signal, the FIFO-passed subcode sync and relates the position of the subcode sync to the audio data (DAC output). This flag may also be used in a super FIFO or in the synchronization of different players. The output flags can be made available at bit 4 of the EBU data format (LSB of the 24-bit data word), if selected by register A. handbook, full pagewidth 33.9/n s F8 11.3/n s F1 F2 F3 F4 F5 F6 F7 F8 33.9/n s F1 MBG425 n = disc speed. Fig.9 Flag output timing diagram. 1998 Jul 06 13 Philips Semiconductors Product specification Digital servo processor and Compact Disc decoder (CD7) Table 2 F1 0 1 x x x x x x x x x x x x x x 7.6.2 Output flags F2 x x 0 0 1 1 x x x x x x x x x x F3 x x 0 1 0 1 x x x x x x x x x x F4 x x x x x x 0 0 0 0 1 1 x x x x F5 x x x x x x 0 0 1 1 0 1 x x x x F6 x x x x x x x x x x x x 0 0 1 1 F7 x x x x x x x x x x x x 0 1 0 1 F8 x x x x x x 0 1 0 1 0 1 x x x x no absolute time sync absolute time sync C1 frame contained no errors C1 frame contained 1 error C1 frame contained 2 errors C1 frame uncorrectable C2 frame contained no errors C2 frame contained 1 error C2 frame contained 2 errors C2 frame contained 3 errors C2 frame contained 4 errors C2 frame uncorrectable no interpolations at least one 1 sample interpolation at least one hold and no interpolations DESCRIPTION SAA7373 at least one hold and one 1 sample interpolation These attenuations do not include the sample-and-hold at the external DAC output or the DAC post filter. When using the oversampling filter, the output level is scaled -0.5 dB down, to avoid overflow on full-scale sine wave inputs (0 to 20 kHz). Table 3 Filter specification STOP BAND - - 24 kHz 24 to 27 kHz 27 to 35 kHz 35 to 64 kHz 64 to 68 kHz 68 kHz 69 to 88 kHz ATTENUATION 0.001 dB 0.03 dB 25 dB 38 dB 40 dB 50 dB 31 dB 35 dB 40 dB C2FAIL The C2FAIL pin indicates that invalid data has occurred on the I2S-bus interface. However, due to the structure of the corrector it is impossible to determine which byte has failed. C2FAIL will go LOW for (140/n) s when invalid data is detected, this data may then occur (15/n) ms before or after the pin is activated. 7.7 7.7.1 Audio functions DE-EMPHASIS AND PHASE LINEARITY PASS BAND 0 to 9 kHz 19 to 20 kHz - - - - - - - When pre-emphasis is detected in the Q-channel subcode, the digital filter automatically includes a de-emphasis filter section. When de-emphasis is not required, a phase compensation filter section controls the phase of the digital oversampling filter to 1 within the band 0 to 16 kHz. With de-emphasis the filter is not phase linear. If the de-emphasis signal is set to be available at V5, selected via register D, then the de-emphasis filter is bypassed. 7.7.2 DIGITAL OVERSAMPLING FILTER The SAA7373 contains a 2 to 4 times oversampling IIR filter. The filter specification of the 4 times oversampling filter is given in Table 3. 1998 Jul 06 14 Philips Semiconductors Product specification Digital servo processor and Compact Disc decoder (CD7) 7.7.3 CONCEALMENT SAA7373 A 1 sample linear interpolator becomes active if a single sample is flagged as erroneous but cannot be corrected. The erroneous sample is replaced by a level midway between the preceding and following samples. Left and right channels have independent interpolators. If more than one consecutive non-correctable sample is found, the last good sample is held. A 1 sample linear interpolation is then performed before the next good sample (see Fig.10). In CD ROM modes (i.e. the DAC interface is selected to be in a CD ROM format) concealment is not executed. 7.7.4 MUTE, FULL SCALE, ATTENUATION AND FADE Fade: activates a 128 stage counter which allows the signal to be scaled up/down by 0.07 dB steps 128 = full scale. 120 = -0.5 dB (i.e. full scale if oversampling filter used). 32 = -12 dB. 0 = mute. 7.7.5 PEAK DETECTOR A digital level controller is present on the SAA7373 which performs the functions of soft mute, full scale, attenuation and fade; these are selected via register 0: Mute: signal reduced to 0 in a maximum of 128 steps; (3/n) ms. Attenuate: signal scaled by -12 dB. Full scale: ramp signal back to 0 dB level. From mute takes (3/n) ms. The peak detector measures the highest audio level (absolute value) on positive peaks for left and right channels. The 8 most significant bits are output in the Q-channel data in place of the CRC bits. Bits 81 to 88 contain the left peak value (bit 88 = MSB) and bits 89 to 96 contain the right peak value (bit 96 = MSB). The values are reset after reading Q-channel data via SDA. Interpolation Hold Interpolation OK Error OK Error Error Error OK OK MGA372 Fig.10 Concealment mechanism. 1998 Jul 06 15 Philips Semiconductors Product specification Digital servo processor and Compact Disc decoder (CD7) 7.8 DAC interface SAA7373 The SAA7373 is compatible with a wide range of digital-to-analog converters (DACs). Eleven formats are supported and are given in Table 4. Figures 11 and 12 show the Philips I2S-bus and the EIAJ data formats respectively. When the decoder is operated in lock-to-disc mode, the SCLK frequency is dependent on the disc speed factor `d'. All formats are MSB first and fs is (44.1 x n) kHz. The polarity of the WCLK and the data can be inverted; selectable by register 7. It should be noted that EF is only a defined output in CD ROM and 1fs modes. Table 4 DAC interface formats SAMPLE FREQUENCY fs fs fs fs fs 4fs 4fs 4fs 2fs 2fs 2fs NUMBER OF BITS 16 16 16/18(1) 16 18 16 18 18 16 18 18 SCLK (MHz) 2.1168 x n 2.1168 x n 2.1168 x n 2.1168 x n 2.1168 x n 8.4672 x n 8.4672 x n 8.4672 x n 4.2336 x n 4.2336 x n 4.2336 x n FORMAT CD ROM (I2S-bus) CD ROM (EIAJ) Philips I2S-bus; 16/18 bits(1) EIAJ 16 bits EIAJ 18 bits EIAJ 16 bits EIAJ 18 bits Philips I2S-bus; 18 bits EIAJ 16 bits EIAJ 18 bits Philips I2S-bus; 18 bits INTERPOLATION no no yes yes yes yes yes yes yes yes yes REGISTER 3 1010 1011 1110 0010 0110 0000 0100 1100 0011 0111 1111 Note 1. In this mode the first 16 bits contain data, but if any of the fade, attenuate or de-emphasis filter functions are activated then the first 18 bits contain data. 1998 Jul 06 16 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... 1998 Jul 06 SCLK DATA 1 0 15 14 1 0 15 14 LEFT CHANNEL DATA (WCLK NORMAL POLARITY) WCLK EF LSB error flag (CD-ROM AND Ifs MODES ONLY) MSB error flag LSB error flag MSB error flag MBG424 Philips Semiconductors Digital servo processor and Compact Disc decoder (CD7) Fig.11 Philips I2S-bus data format (16-bit word length shown). 17 SCLK DATA 0 17 LEFT CHANNEL DATA WCLK EF (CD-ROM AND Ifs MODES ONLY) 0 17 MSB error flag LSB error flag MSB error flag MBG423 Product specification SAA7373 Fig.12 EIAJ data format (18-bit word length shown). Philips Semiconductors Product specification Digital servo processor and Compact Disc decoder (CD7) 7.9 EBU interface 7.9.1 FORMAT SAA7373 The bi-phase mark digital output signal at pin DOBM is in accordance with the format defined by the IEC958 specification. Three different modes can be selected via register A: * DOBM pin held LOW * Data taken before concealment, mute and fade (must always be used for CD ROM modes) * Data taken after concealment, mute and fade. Table 5 Format BITS 0 to 3 4 to 7 4 8 to 27 28 29 30 31 Description of Table 5 - not used; normally zero The digital audio output consists of 32-bit words (`subframes') transmitted in bi-phase mark code (two transitions for a logic 1 and one transition for a logic 0). Words are transmitted in blocks of 384. Table 5 gives the formats. FUNCTION Sync Auxiliary Error flags Audio sample Validity flag User data Channel status Parity bit Table 6 DESCRIPTION CFLG error and interpolation flags when selected by register A first 4 bits not used (always zero). 2's compliment. LSB = bit 12, MSB = bit 27 valid = logic 0 used for subcode data (Q-to-W) control bits and category code even parity for bits 4 to 30 FUNCTION Sync DESCRIPTION The sync word is formed by violation of the bi-phase rule and therefore does not contain any data. Its length is equivalent to 4 data bits. The 3 different sync patterns indicate the following situations: sync B: start of a block (384 words), word contains left sample; sync M: word contains left sample (no block start) and sync W: word contains right sample. Left and right samples are transmitted alternately. Audio samples are flagged (bit 28 = 1) if an error has been detected but was uncorrectable. This flag remains the same even if data is taken after concealment. Subcode bits Q-to-W from the subcode section are transmitted via the user data bit. This data is asynchronous with the block rate. The channel status bit is the same for left and right words. Therefore a block of 384 words contains 192 channel status bits. The category code is always CD. The bit assignment is given in Table 7. Audio sample Validity flag User data Channel status 1998 Jul 06 18 Philips Semiconductors Product specification Digital servo processor and Compact Disc decoder (CD7) Table 7 Bit assignment BITS 0 to 3 4 to 7 8 to 15 28 to 29 16 to 27 and 30 to 191 DESCRIPTION SAA7373 FUNCTION Control Reserved mode Category code Clock accuracy Remaining copy of CRC checked Q-channel control bits 0 to 3; bit 2 is logic 1 when copy permitted; bit 3 is logic 1 when recording has pre-emphasis always zero CD: bit 8 = logic 1, all other bits = logic 0 set by register A; 10 = level I; 00 = level II; 01 = level III always zero 7.10 KILL circuit 7.11 Audio features off The KILL circuit detects digital silence by testing for an all-zero or all-ones data word in the left or right channel before the digital filter. The output is switched active LOW when silence has been detected for at least 250 ms, or if mute is active, or in CD ROM modes. Two modes are available which can be selected by register C: 1 pin kill: KILL active LOW indicates silence detected on both left and right channels. 2 pin kill: KILL active LOW indicates silence detected on left channel. V3 active LOW indicates silence detected on right channel. It should be noted that when mute is active or in CD ROM modes the output(s) are switched LOW. The audio features can be turned off (selected by register E) which affects the following functions: * Digital filter, fade, peak detector, KILL circuit (but outputs KILL, V3 still active) are disabled * V5 (if selected to be the de-emphasis flag output) and the EBU outputs become undefined. It should be noted that the EBU output should be set LOW prior to switching the audio features off and after switching audio features back on a full-scale command should be given. 1998 Jul 06 19 Philips Semiconductors Product specification Digital servo processor and Compact Disc decoder (CD7) 7.12 The VIA interface SAA7373 The SAA7373 has five pins that can be reconfigured for different applications (see Table 8). Table 8 Pin applications PIN NUMBER 62 TYPE input CONTROL REGISTER ADDRESS 1100 - V2 V3 63 42 input output - 1100 - - V4 41 output 1101 - - - V5 40 output 1101 - - 7.13 7.13.1 Spindle motor control MOTOR OUTPUT MODES CONTROL REGISTER DATA xxx1 xxx0 - xx0x x01x x11x 0000 xx01 xx10 xx11 01xx 10xx 11xx FUNCTION external off-track signal input internal off-track signal used, input may be read via decoder status bit; selected via register 2 input may be read via decoder status bit; selected via register 2 KILL output for right channel output = 0 output = 1 4-line motor drive (using V4 and V5) Q-to-W subcode output output = 0 output = 1 de-emphasis output (active HIGH) output = 0 output = 1 PIN NAME V1 7.13.1.1 Pulse density output mode The spindle motor speed is controlled by a fully integrated digital servo. Address information from the internal 8 frame FIFO and disc speed information are used to calculate the motor control output signals. Several output modes, selected by register 6, are supported: * Pulse density, 2-line (true complement output), (1 x n) MHz sample frequency * PWM output, 2-line, (22.05 x n) kHz modulation frequency * PWM output, 4-line, (22.05 x n) kHz modulation frequency * CDV motor mode. In the pulse density mode the motor output pin (MOTO1) is the pulse density modulated motor output signal. A 50% duty factor corresponds with the motor not actuated, higher duty factors mean acceleration, lower mean braking. In this mode, the MOTO2 signal is the inverse of the MOTO1 signal. Both signals change state only on the edges of a (1 x n) MHz internal clock signal. Possible application diagrams are illustrated in Fig.13. 7.13.1.2 PWM output mode (2-line) In the PWM mode the motor acceleration signal is put in pulse-width modulation form on the MOTO1 output. The motor braking signal is pulse-width modulated on the MOTO2 output. The timing is illustrated in Fig.14. A typical application diagram is illustrated in Fig.15. 1998 Jul 06 20 Philips Semiconductors Product specification Digital servo processor and Compact Disc decoder (CD7) SAA7373 22 k MOTO1 10 nF VSS 22 k + - M + - VSS MOTO2 10 nF VDD 22 k 22 k MOTO1 22 k VSS 10 nF VSS + - 22 k 22 k M V SS VDD MGA363 - 1 Fig.13 Motor pulse density application diagrams. t rep = 45 s MOTO1 MOTO2 t dead 240 ns Accelerate Brake MGA366 Fig.14 2-line PWM mode timing. + M 10 100 nF MOTO1 MOTO2 VSS MGA365 - 2 Fig.15 Motor 2-line PWM mode application diagram. 1998 Jul 06 21 Philips Semiconductors Product specification Digital servo processor and Compact Disc decoder (CD7) 7.13.1.3 PWM output mode (4-line) SAA7373 Using two extra outputs from the versatile pins interface, it is possible to use the SAA7373 with a 4-input motor bridge. The timing is illustrated in Fig.16. A typical application diagram is illustrated in Fig.17. t rep = 45 s MOTO1 MOTO2 V4 V5 t dead 240 ns t ovl = 240 ns MGA367 - 1 Accelerate Brake Fig.16 4-line PWM mode timing. + V4 V5 M 10 100 nF MOTO1 MOTO2 VSS MGA364 - 2 Fig.17 Motor 4-line PWM mode application diagram. 1998 Jul 06 22 Philips Semiconductors Product specification Digital servo processor and Compact Disc decoder (CD7) 7.13.1.4 CDV/CAV output mode SAA7373 In the CDV motor mode, the FIFO position will be put in pulse-width modulated form on the MOTO1 pin [carrier frequency (300 x d) Hz], where `d' is the disc speed factor. The PLL frequency signal will be put in pulse-density modulated form (carrier frequency 4.23 x n MHz) on the MOTO2 pin. The integrated motor servo is disabled in this mode. The PWM signal on MOTO1 corresponds to a total memory space of 20 frames, therefore the nominal FIFO position (half full) will result in a PWM output of 60%. In the lock to-disc (CAV) mode the CDV motor mode is the only mode that can be used to control the motor. 7.13.2 SPINDLE MOTOR OPERATING MODES This voltage can be programmed as a percentage of the maximum possible voltage, via register 6, to limit current drain during start and stop. The following power limits are possible; 100% (no power limit), 75%, 50%, or 37% of maximum. 7.13.3 LOOP CHARACTERISTICS The gain and crossover frequencies of the motor control loop can be programmed via registers 4 and 5. The following parameter values are possible; Gains: 3.2, 4.0, 6.4, 8.0, 12.8, 16, 25.6 and 32 Crossover frequency f4: 0.5 x n Hz, 0.7 x n Hz, 1.4 x n Hz, 2.8 x n Hz Crossover frequency f3: 0.85 x n Hz, 1.71 x n Hz, 3.42 x n Hz It should be noted that the crossover frequencies f3 and f4 are scaled with the overspeed factor `n' whereas the gains are not. 7.13.4 FIFO OVERFLOW The operation modes of the motor servo is controlled by register 1 (see Table 9). In the SAA7373 decoder there is an anti-wind-up mode for the motor servo, selected via register 1. When the anti-wind-up mode is activated the motor servo integrator will hold if the motor output saturates. 7.13.2.1 Power limit In start mode 1, start mode 2, stop mode 1 and stop mode 2, a fixed positive or negative voltage is applied to the motor. Table 9 Operating modes If FIFO overflow occurs during Play mode (e.g. as a result of motor rotational shock), the FIFO will be automatically reset to 50% and the audio interpolator tries to conceal as much as possible to minimise the effect of data loss. MODE Start mode 1 Start mode 2 DESCRIPTION The disc is accelerated by applying a positive voltage to the spindle motor. No decisions are involved and the PLL is reset. No disc speed information is available for the microcontroller. The disc is accelerated as in start mode 1, however the PLL will monitor the disc speed. When the disc reaches 75% of its nominal speed, the controller will switch to jump mode. The motor status signals selectable via register 2 are valid. Motor servo enabled but FIFO kept reset at 50%, integrator is held. The audio is muted but it is possible to read the subcode. It should be noted that in the CD ROM modes the data, on EBU and the I2S-bus is not muted. Similar to jump mode but motor integrator is kept at zero. Used for long jumps where there is a large change in disc speed. FIFO released after resetting to 50%. Audio mute released. Disc is braked by applying a negative voltage to the motor. No decisions are involved. The disc is braked as in stop mode 1 but the PLL will monitor the disc speed. As soon as the disc reaches 12% (or 6%, depending on the programmed brake percentage, via register E) of its nominal speed, the MOTSTOP status signal will go HIGH and switch the motor servo to Off mode. Motor not steered. Jump mode Jump mode 1 Play mode Stop mode 1 Stop mode 2 Off mode 1998 Jul 06 23 Philips Semiconductors Product specification Digital servo processor and Compact Disc decoder (CD7) SAA7373 MGA362 - 2 G f4 f3 BW f Fig.18 Motor servo mode diagram. 7.14 7.14.1 Servo part DIODE SIGNAL PROCESSING current generated by the external resistor on IrefT. In the application VRL is connected to VSSA1. The maximum input currents for a range of resistors is given Table 10. Table 10 Maximum current input DIODE INPUT CURRENT RANGE RIrefT (k) 220 240 270 300 330 360 390 430 470 510 560 620 D1 TO D4 (A) 10.909 10.000 8.889 8.000 7.273 6.667 6.154 5.581 5.106 4.706 4.286 3.871 R1 AND R2 (A) 5.455 5.000 4.444 4.000 3.636 3.333 3.077 2.791 2.553 2.353 2.143 1.935 The photo detector in conventional two-stage three-beam compact disc systems normally contains six discrete diodes. Four of these diodes (three for single foucault systems) carry the central aperture signal (CA) while the other two diodes (satellite diodes) carry the radial tracking information. The CA signal is processed into an HF signal (for the decoder function) and LF signal (information for the focus servo loop) before it is supplied to the SAA7373. The analog signals from the central and satellite diodes are converted into a digital representation using analog-to-digital converters (ADCs). The ADCs are designed to convert unipolar currents into a digital code. The dynamic range of the input currents is adjustable within a given range, which is dependent on the value of external resistor connected to pin IrefT. The maximum current for the central diodes and satellite diodes is given in the following formulae; 2.4 x 10 6 I in ( max, central ) = ----------------------- A R IrefT 1.2 x 10 6 I in ( max, satellite ) = ----------------------- A R IrefT The VRH voltage is internally generated by control circuitry which ensures that the VRH voltage is adjusted depending on the spread of internal capacitors, using the reference 1998 Jul 06 24 This mode of VRH automatic adjustment can be selected by the preset latch command. Alternatively, the dynamic range of the input currents can be made dependent on the ADC reference voltages VRL and VRH. The maximum current for the central diodes and satellite diodes is given in the following formulae; Philips Semiconductors Product specification Digital servo processor and Compact Disc decoder (CD7) I in ( max, central ) = f sys x ( V RH - V RL ) x 1.0 x 10 -6 SAA7373 A A The error signal, FEn, is further processed by a proportional integral and differential (PID) filter section. A Focus OK (FOK) flag is generated by means of the central aperture signal and an adjustable reference level. This signal is used to provide extra protection for the track-loss (TL) generation, the focus start-up procedure and the drop out detection. The radial or tracking error signal is generated by the satellite detector signals R1 and R2. The radial error signal can be formulated as follows; RE s = ( R1 - R2 ) x re_gain + ( R1 - R2 ) x re_offset where the index `s' indicates the automatic scaling operation which is performed on the radial error signal. This scaling is necessary to avoid non-optimum dynamic range usage in the digital representation and reduces the radial bandwidth spread. Furthermore, the radial error signal will be made free from offset during start up of the disc. The four signals from the central aperture detectors, together with the satellite detector signals generate a track position signal (TPI) which can be formulated as follows; TPI = sign [(D1 + D2 + D3 + D4) - (R1 + R2) x sum_gain] Where the weighting factor sum_gain is generated internally by the SAA7373 during initialization. I in ( max, satellite ) = f sys x ( V RH - V RL ) x 0.5 x 10 Where fsys = 4.2336 MHz. -6 VRH is generated internally, and there are 32 levels which can be selected under software control via the preset latch command. With this command the VRH voltage can be set to 2.5 V then modified, decremented one level or incremented, by resending the command the required number of times. In the application VRL is connected to VSSA1. 7.14.2 SIGNAL CONDITIONING The digital codes retrieved from the ADCs are applied to logic circuitry to obtain the various control signals. The signals from the central aperture diodes are processed to obtain a normalised focus error signal. D1 - D2 D3 - D4 FE n = --------------------- - --------------------D1 + D2 D3 + D4 where the detector set-up is assumed as shown in Fig.19. In the event of single Foucault focusing method, the signal conditioning can be switched under software control such that the signal processing is as follows; D1 - D2 FE n = 2 x --------------------D1 + D2 handbook, full pagewidth SATELLITE DIODE R1 SATELLITE DIODE R1 SATELLITE DIODE R1 D1 D3 D2 D2 D4 D1 D3 D1 D2 D3 D4 SATELLITE DIODE R2 SATELLITE DIODE R2 SATELLITE DIODE R2 single Foucault astigmatic focus double Foucault MBG422 Fig.19 Detector arrangement. 1998 Jul 06 25 Philips Semiconductors Product specification Digital servo processor and Compact Disc decoder (CD7) 7.14.3 FOCUS SERVO SYSTEM SAA7373 7.14.3.1 Focus start-up action of the PID can be switched at the same time as the gain switching is performed. Five initially loaded coefficients influence the start-up behaviour of the focus controller. The automatically generated triangle voltage can be influenced by 3 parameters; for height (ramp_height) and DC offset (ramp_offset) of the triangle and its steepness (ramp_incr). For protection against false focus point detections two parameters are available which are an absolute level on the CA-signal (CA_start) and a level on the FEn signal (FE_start). When this CA level is reached the FOK signal becomes true. If the FOK signal is true and the level on the FEn signal is reached, the focus PID is enabled to switch on when the next zero crossing is detected in the FEn signal. 7.14.3.6 Focus automatic gain control loop The loop gain of the focus control loop can be corrected automatically to eliminate tolerances in the focus loop. This gain control injects a signal into the loop which is used to correct the loop gain. Since this decreases the optimum performance, the gain control should only be activated for a short time (for example, when starting a new disc). 7.14.4 RADIAL SERVO SYSTEM 7.14.4.1 Level initialization 7.14.3.2 Focus position control loop The focus control loop contains a digital PID controller which has 5 parameters which are available to the user. These coefficients influence the integrating (foc_int), proportional (foc_lead_length, part of foc_parm3) and differentiating (foc_pole_lead, part of foc_parm1) action of the PID and a digital low-pass filter (foc_pole_noise, part of foc_parm2) following the PID. The fifth coefficient foc_gain influences the loop gain. During start-up an automatic adjustment procedure is activated to set the values of the radial error gain (re_gain), offset (re_offset) and satellite sum gain (sum_gain) for TPI level generation. The initialization procedure runs in a radial open loop situation and is 300 ms. This start-up time period may coincide with the last part of the motor start-up time period. Automatic gain adjustment: as a result of this initialization the amplitude of the RE signal is adjusted to within 10% around the nominal RE amplitude. Offset adjustment: the additional offset in RE due to the limited accuracy of the start-up procedure is less than 50 nm. TPI level generation: the accuracy of the initialization procedure is such that the duty factor range of TPI becomes 0.4 < duty factor < 0.6 (definition of duty factor = TPI HIGH/TPI period). 7.14.3.3 Drop-out detection This detector can be influenced by one parameter (CA_drop). The FOK signal will become false and the integrator of the PID will hold if the CA signal drops below this programmable absolute CA level. When the FOK signal becomes false it is assumed, initially, to be caused by a black dot. 7.14.4.2 Sledge control The microcontroller can move the sledge in both directions via the steer sledge command. 7.14.3.4 Focus loss detection and fast restart 7.14.4.3 Tracking control Whenever FOK is false for longer than approximately 3 ms, it is assumed that the focus point is lost. A fast restart procedure is initiated which is capable of restarting the focus loop within 200 to 300 ms depending on the programmed coefficients of the microcontroller. 7.14.3.5 Focus loop gain switching The actuator is controlled using a PID loop filter with user defined coefficients and gain. For stable operation between the tracks, the S-curve is extended over 0.75 of the track. On request from the microcontroller, S-curve extension over 2.25 tracks is used, automatically changing to access control when exceeding those 2.25 tracks. Both modes of S-curve extension make use of a track-count mechanism. In this mode, track counting results in an `automatic return-to-zero track', to avoid major music rhythm disturbances in the audio output for improved shock resistance. The gain of the focus control loop (foc_gain) can be multiplied by a factor of 2 or divided by a factor of 2 during normal operation. The integrator value of the PID is corrected accordingly. The differentiating (foc_pole_lead) 1998 Jul 06 26 Philips Semiconductors Product specification Digital servo processor and Compact Disc decoder (CD7) The sledge is continuously controlled, or provided with step pulses to reduce power consumption using the filtered value of the radial PID output. Alternatively, the microcontroller can read the average voltage on the radial actuator and provide the sledge with step pulses to reduce power consumption. Filter coefficients of the continuous sledge control can be preset by the user. SAA7373 Radial automatic gain control loop 7.14.4.5 The loop gain of the radial control loop can be corrected automatically to eliminate tolerances in the radial loop. This gain control injects a signal into the loop which is used to correct the loop gain. Since this decreases the optimum performance, the gain control should only be activated for a short time (for example, when starting a new disc). This gain control differs from the level initialization. The level initialization should be performed first. The disadvantage of using the level initialization without the gain control is that only tolerances from the front-end are reduced. 7.14.5 OFF-TRACK COUNTING 7.14.4.4 Access The access procedure is divided into two different modes (see Table 11), depending on the requested jump size. Table 11 Access modes ACCESS TYPE JUMP SIZE(1) ACCESS SPEED decreasing velocity maximum power to sledge(1) Actuator jump 1 - brake_distance Sledge jump brake_distance - 32768 The track position signal (TPI) is a flag which is used to indicate whether the radial spot is positioned on the track, with a margin of 14 of the track-pitch. In combination with the radial polarity flag (RP) the relative spot position over the tracks can be determined. These signals are, however, afflicted with some uncertainties caused by; * Disc defects such as scratches and fingerprints * The HF information on the disc, which is considered as noise by the detector signals. In order to determine the spot position with sufficient accuracy, extra conditions are necessary to generate a track loss signal (TL) and an off-track counter value. These extra conditions influence the maximum speed and this implies that, internally, one of the following three counting states is selected; 1. Protected state: used in normal play situations. A good protection against false detection caused by disc defects is important in this state. 2. Slow counting state: used in low velocity track jump situations. In this state a fast response is important rather than the protection against disc defects (if the phase relationship between TL and RP of 12 radians is affected too much, the direction cannot then be determined accurately). 3. Fast counting state: used in high velocity track jump situations. Highest obtainable velocity is the most important feature in this state. Note 1. Microcontroller presettable. The access procedure makes use of a track counting mechanism, a velocity signal based on a fixed number of tracks passed within a fixed time interval, a velocity set point calculated from the number of tracks to go and a user programmable parameter indicating the maximum sledge performance. If the number of tracks remaining is greater than the brake_distance then the sledge jump mode should be activated, or, the actuator jump should be performed. The requested jump size together with the required sledge breaking distance at maximum access speed defines the brake_distance value. During the actuator jump mode, velocity control with a PI controller is used for the actuator. The sledge is then continuously controlled using the filtered value of the radial PID output. All filter parameters (for actuator and sledge) are user programmable. In the sledge jump mode maximum power (user programmable) is applied to the sledge in the correct direction while the actuator becomes idle (the contents of the actuator integrator leaks to zero just after the sledge jump mode is initiated). 1998 Jul 06 27 Philips Semiconductors Product specification Digital servo processor and Compact Disc decoder (CD7) 7.14.6 DEFECT DETECTION SAA7373 handbook, full pagewidth sat1 + - DECIMATION FILTER FAST FILTER SLOW FILTER DEFECT GENERATION PROGRAMMABLE HOLD-OFF defect output sat2 MBG421 Fig.20 Block diagram of defect detector. A defect detection circuit is incorporated into the SAA7373. If a defect is detected, the radial and focus error signals may be zeroed, resulting in better playability. The defect detector can be switched off, applied only to focus control or applied to both focus and radial controls under software control (part of foc_parm1). The defect detector (see Fig.20) has programmable set points selectable by the parameter defect_parm. 7.14.7 OFF-TRACK DETECTION been crossed during time defined by jumpwatchtime parameter. 6. Autosequencer state change. 7. Autosequencer error. 8. Subcode interface blocked: the internal decoder interface is being used. It should be noted that if the STATUS pin output is selected via register 2 and either the microcontroller writes a different value to register 2 or the decoder interface is enabled then the STATUS output will change. During active radial tracking, off-track detection has been realised by continuously monitoring the off-track counter value. The off-track flag becomes valid whenever the off-track counter value is not equal to zero. Depending on the type of extended S-curve, the off-track counter is reset after 0.75 extend or at the original track in the 2.25 track extend mode. 7.14.8 HIGH-LEVEL FEATURES 7.14.8.2 Decoder interface The decoder interface allows registers 0 to F to be programmed and subcode Q-channel data to be read via servo commands. The interface is enabled/disabled by the preset latch command (and the xtra_preset parameter). 7.14.8.3 Automatic error handling 7.14.8.1 Interrupt mechanism and STATUS pin Three watchdogs are present: 1. Focus: detects focus drop out of longer than 3 ms, sets focus lost interrupt, switches off radial and sledge servos, disables drive to disc motor. 2. Radial play: started when radial servo is on-track mode and a first subcode frame is found. Detects when maximum time between two subcode frames exceeds time set by playwatchtime parameter; then sets radial error interrupt, switches radial and sledge servos off, puts disc motor in jump mode. 3. Radial jump: active when radial servo in long jump or short jump modes. Detects when the off-track counter value decreases by less than 4 tracks between two readings (time interval set by jumpwatchtime parameter); then sets radial jump error, switches radial and sledge servos off to cancel jump. The focus watchdog is always active, the radial watchdogs are selectable via the radcontrol parameter. The STATUS pin is an output which is active LOW, its output is selected by register 7 to be either the status bit (active LOW) selected by register 2 (only available in 4-wire bus mode) or the interrupt signal generated by the servo part. 8 signals from the interrupt status register are selectable from the servo part via the interrupt_mask parameter. The interrupt is reset by sending the read high-level status command. The 8 signals are listed below: 1. Focus lost: drop out of longer than 3 ms. 2. Subcode ready. 3. Subcode absolute seconds changed. 4. Subcode discontinuity detected: new subcode time before previous subcode time, or more than 10 frames later than previous subcode time. 5. Radial error: during radial on-track, no new subcode frame occurs within time defined by playwatchtime parameter. During radial jump, less than 4 tracks have 1998 Jul 06 28 Philips Semiconductors Product specification Digital servo processor and Compact Disc decoder (CD7) 7.14.8.4 Automatic sequencers and timer interrupts SAA7373 Two automatic sequencers are implemented (and must be initialized after power-on): 1. Autostart sequencer: controls the start-up of focus, radial and motor. 2. Autostop sequencer: brakes the disc and shuts down servos. When the automatic sequencers are not used it is possible to generate timer interrupts, defined by the time_parameter coefficient. During reset (i.e. RESET pin is held LOW) the RA, FO and SL pins are high-impedance. 7.14.10 LASER INTERFACE The LDON pin (open-drain output) is used to switch the laser off and on. When the laser is on the output is high impedance. The action of the LDON pin is controlled by the xtra_preset parameter; the pin is automatically driven if the focus control loop is active. 7.14.11 RADIAL SHOCK DETECTOR The shock detector (see Fig.21) can be switched on during normal track following, and detects within an adjustable frequency whether disturbances in the radial spot position relative to the track exceed an adjustable level (controlled by shock_level). Every time the radial tracking error (RE) exceeds this level the radial control bandwidth is switched to twice its original bandwidth and the loop gain is increased by a factor of 4. The shock detection level is adjustable in 16 steps from 0 to 100% of the traverse radial amplitude which is sent to an amplitude detection unit via an adjustable band-pass filter (controlled by sledge_parm1); lower corner frequency can be set at either 0 or 20 Hz, and upper corner frequency at 750 or 1850 Hz. The shock detector is switched off automatically during jump mode. 7.14.8.5 High-level status The read high-level status command can be used to obtain the interrupt, decoder, autosequencer status registers and the motor start time. Use of the read high-level status command clears the interrupt status register, and re-enables the subcode read via a servo command. 7.14.9 DRIVER INTERFACE The control signals (pins RA, FO and SL) for the mechanism actuators are pulse density modulated. The modulating frequency can be set to either 1.0584 MHz (DSD mode) or 2.1168 MHz; controlled via the xtra_preset parameter. An analog representation of the output signals can be achieved by connecting a first-order low-pass filter to the outputs. handbook, full pagewidth RE HIGH-PASS FILTER (0 or 20 Hz) LOW-PASS FILTER (750 or 1850 Hz) AMPLITUDE DETECTION SHOCK OUTPUT MGC914 Fig.21 Block diagram of radial shock detector. 1998 Jul 06 29 Philips Semiconductors Product specification Digital servo processor and Compact Disc decoder (CD7) 7.15 Microcontroller interface SAA7373 Communication on the microcontroller interface can be set-up in two different modes: 1. 4-wire bus mode: protocol compatible with SAA7345 (CD6) and TDA1301 (DSIC2) where: a) SCL = serial bit clock b) SDA = serial data c) RAB = R/W control and data strobe (active HIGH) for writing to registers 0 to F, reading status bit selected via register 2 and reading Q-channel subcode. d) SILD = R/W control and data strobe (active LOW) for servo commands. 2. I2C-bus mode: protocol where SAA7373 behaves as slave device, activated by setting RAB = HIGH and SILD = LOW where: a) I2C-bus slave address (write mode) = 30H. b) I2C-bus slave address (read mode) = 31H. c) Maximum data transfer rate = 400 kbits/s It should be noted that only servo commands can be used therefore, writing to registers 0 to F, reading decoder status and reading Q-channel subcode data must be performed by servo commands. 7.15.1 MICROPROCESSOR INTERFACE (4-WIRE BUS MODE) I2C-bus MOTSTART1: HIGH if motor is turning at 75% or more of nominal speed. MOTSTART2: HIGH if motor is turning at 50% or more of nominal speed. MOTSTOP: HIGH if motor is turning at 12% or less of nominal speed. Can be set to indicate 6% or less (instead of 12% or less) via register E. PLL Lock: HIGH if sync coincidence signals are found. V1: follows input on V1 pin. V2: follows input on V2 pin. MOTOR-OV: HIGH if the motor servo output stage saturates. FIFO-OV: HIGH if FIFO overflows. SHOCK: MOTSTART2 + PLL Lock + MOTOR-OV + FIFO-OV + servo interrupt signal + OTD (HIGH if shock detected). LA-SHOCK: latched SHOCK signal. The status read protocol is shown in Fig.24. It should be noted that SILD must be held HIGH. 7.15.1.4 Reading Q-channel subcode To read the Q-channel subcode direct in the 4-wire bus mode, the SUBQREADY-I signal should be selected as status signal. The subcode read protocol is illustrated in Fig.25. It should be noted that SILD must be held HIGH; after subcode read starts, the microcontroller may take as long as it wants to terminate the read operation; when enough subcode has been read (1 to 96 bits), terminate reading by pulling RAB LOW. Alternatively, the Q-channel subcode can be read using a servo command as follows: * Use the read high-level status command to monitor the subcode ready signal. * Send the read subcode command, and read the required number of bytes (up to 12). * Send the read high-level status command; to re-enable the decoder interface. 7.15.1.1 Writing data to registers 0 to F The sixteen 4-bit programmable configuration registers, 0 to F (see Table 12), can be written to via the microcontroller interface using the protocol shown in Fig.22. It should be noted that SILD must be held HIGH; A3 to A0 identifies the register number and D3 to D0 is the data; the data is latched into the register on the LOW-to-HIGH transition of RAB. 7.15.1.2 Writing repeated data to registers 0 to F The same data can be repeated several times (e.g. for a fade function) by applying extra RAB pulses as shown in Fig.23. It should be noted that SCL must stay HIGH between RAB pulses. 7.15.1.5 Behaviour of the SUBQREADY-I signal 7.15.1.3 Reading decoder status information on SDA There are several internal status signals, selected via register 2, which can be made available on the SDA line;: SUBQREADY-I: LOW if new subcode word is ready in Q-channel register. 1998 Jul 06 30 When the CRC of the Q-channel word is good, and no subcode is being read, the SUBQREADY-I status signal will react as shown in Fig.26. When the CRC is good and the subcode is being read, the timing in Fig.27 applies. Philips Semiconductors Product specification Digital servo processor and Compact Disc decoder (CD7) If t1 (SUBQREADY-I status LOW to end of subcode read) is below (2.6/n) ms, then t2 = (13.1/n) ms [i.e. the microcontroller can read all subcode frames if it completes the read operation within (2.6/n) ms after the subcode is ready]. If this criterion is not met, it is only possible to guarantee that t3 will be below (26.2/n) ms (approximately). If subcode frames with failed CRCs are present, the t2 and t3 times will be increased by (13.1/n) ms for each defective subcode frame. It should be noted that in the lock-to-disc mode `n' is replaced by `d', which is the disc speed factor. 7.15.2 SAA7373 MICROCONTROLLER INTERFACE (I2C-BUS MODE) Bytes are transferred over the interface in groups (i.e. servo commands) of which there are two types: write data commands and read data commands. The sequence for a write data command (that requires 3 data bytes) is as follows; * Send START condition * Send address 30H (write) * Write command byte * Write data byte 1 * Write data byte 2. * Write data byte 3 * Send STOP condition. It should be noted that more than one command can be sent in one write sequence. The sequence for a read data command (that reads 2 data bytes) is as follows; * Send START condition * Send address 30H (write) * Write command byte * Send STOP condition. * Send START condition * Send address 31H (read) * Read data byte 1 * Read data byte 2 * Send STOP condition. It should be noted that the timing constraints specified for the read and write servo commands must still be adhered to. 7.15.1.6 Write servo commands A write data command is used to transfer data (a number of bytes) from the microcontroller, using the protocol shown in Fig.28. The first of these bytes is the command byte and the following are data bytes; the number (between 1 and 7) depends on the command byte. It should be noted that RAB must be held LOW; the command or data is interpreted by the SAA7373 after the HIGH-to-LOW transition of SILD; there must be a minimum time of 70 s between SILD pulses. 7.15.1.7 Writing repeated data in servo commands The same data byte can be repeated by applying extra SILD pulses as shown in Fig.29. SCL must stay HIGH between the SILD pulses. 7.15.1.8 Read servo commands A read data command is used to transfer data (status information) to the microcontroller, using the protocol shown in Fig.30. The first byte written determines the type of command. After this byte a variable number of bytes can be read. It should be noted that RAB must be held LOW; after the end of the command byte (LOW-to-HIGH transition on SILD) there must be a delay of 70 s before reading data is started (i.e the next HIGH-to-LOW transition on SILD); there must be a minimum time of 70 s between SILD pulses. 1998 Jul 06 31 Philips Semiconductors Product specification Digital servo processor and Compact Disc decoder (CD7) SAA7373 RAB (microcontroller) SCL (microcontroller) SDA (microcontroller) SDA (SAA7373) A3 A2 A1 A0 D3 D2 D1 D0 high-impedance MGR325 Fig.22 Microcontroller write protocol for registers 0 to F. RAB (microcontroller) SCL (microcontroller) SDA (microcontroller) SDA (SAA7373) A3 A2 A1 A0 D3 D2 D1 D0 high-impedance MGR326 Fig.23 Microcontroller write protocol for registers 0 to F (repeat mode). RAB (microcontroller) SCL (microcontroller) SDA (microcontroller) high-impedance STATUS MGR327 SDA (SAA7373) Fig.24 Microcontroller read protocol for decoder status on SDA. 1998 Jul 06 32 Philips Semiconductors Product specification Digital servo processor and Compact Disc decoder (CD7) SAA7373 RAB (microcontroller) SCL (microcontroller) SDA (SAA7373) STATUS CRC OK Q1 Q2 Q3 Qn-2 Qn-1 Qn MGR328 Fig.25 Microcontroller protocol for reading Q-channel subcode. RAB (microcontroller) SCL (microcontroller) SDA (SAA7373) high impedance CRC OK CRC OK 10.8/n ms 15.4/n ms 2.3/n ms MGR329 READ start allowed Fig.26 SUBQREADY-I status timing when no subcode is read. 1998 Jul 06 33 Philips Semiconductors Product specification Digital servo processor and Compact Disc decoder (CD7) SAA7373 t2 t1 RAB (microcontroller) SCL (microcontroller) SDA (SAA7373 ) Q1 Q2 Q3 Qn MGR330 t3 Fig.27 SUBQREADY-I status timing when subcode is read. handbook, full pagewidth SILD (microcontroller) SCL (microcontroller) SDA (microcontroller) SDA (SAA7373) high-impedance microcontroller write (one byte: command or data) SILD (microcontroller) SDA (microcontroller) COMMAND DATA1 DATA2 DATA3 MGR331 D7 D6 D5 D4 D3 D2 D1 D0 command or data byte microcontroller write (full command) Fig.28 Microcontroller protocol for write servo commands. 1998 Jul 06 34 Philips Semiconductors Product specification Digital servo processor and Compact Disc decoder (CD7) SAA7373 handbook, full pagewidth SILD (microcontroller) SDA (microcontroller) COMMAND DATA1 MBG413 microcontroller write (full command) Fig.29 Microcontroller protocol for repeated data in write servo commands. handbook, full pagewidth SILD (microcontroller) SCL (microcontroller) SDA (SAA7373) D7 D6 D5 D4 D3 data byte microcontroller read (one data byte) SILD (microcontroller) SDA (SAA7373) SDA (microcontroller) COMMAND MGR332 D2 D1 D0 DATA1 DATA2 DATA3 microcontroller read (full command) Fig.30 Microcontroller protocol for read servo commands. 1998 Jul 06 35 Philips Semiconductors Product specification Digital servo processor and Compact Disc decoder (CD7) 7.15.3 SUMMARY OF FUNCTIONS CONTROLLED BY REGISTERS 0 TO F SAA7373 Table 12 Registers 0 to F REGISTER 0 (fade and attenuation) ADDRESS 0000 DATA 0000 0010 0001 0100 0101 1 (motor mode) 0001 x000 x 001 x010 x011 x100 x101 x111 x110 1xxx 0xxx 2 (status control) 0010 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 3 (DAC output) 0011 1010 1011 1100 1111 1110 0000 0011 0010 0100 0111 0110 mute attenuate full scale step down step up motor off mode motor stop mode 1 motor stop mode 2 motor start mode 1 motor start mode 2 motor jump mode motor play mode motor jump mode 1 anti-windup active anti-windup off status = SUBQREADY-I status = MOTSTART1 status = MOTSTART2 status = MOTSTOP status = PLL Lock status = V1 status = V2 status = MOTOR-OV status = FIFO overflow status = shock detect status = latched shock detect status = latched shock detect reset I2S-bus; I2S-bus; I2S-bus; CD-ROM mode 18-bit; 4fs mode 18-bit; 2fs mode EIAJ; CD-ROM mode FUNCTION INITIAL(1) reset - - - - reset - - - - - - - - reset reset - - - - - - - - - - - - - reset - - - - - - - - I2S-bus; 16-bit; fs mode EIAJ; 16-bit; 4fs EAIJ; 16-bit; 2fs EIAJ; 16-bit; fs EIAJ; 18-bit; 4fs EIAJ; 18-bit; 2fs EIAJ; 18-bit; fs 1998 Jul 06 36 Philips Semiconductors Product specification Digital servo processor and Compact Disc decoder (CD7) REGISTER 4 (motor gain) ADDRESS 0100 DATA x000 x001 x010 x011 x100 x101 x110 x111 0xxx 1xxx 5 (motor bandwidth) 0101 xx00 xx01 xx10 xx11 00xx 01xx 10xx 6 (motor output configuration) 0110 xx00 xx01 xx10 xx11 00xx 01xx 10xx 11xx 7 (DAC output and status control) 0111 xx00 xx10 x0xx x1xx 0xxx 1xxx 8 (PLL loop filter bandwidth) 9 (PLL equalization) 1001 0011 0001 0010 0100 0101 motor gain G = 3.2 motor gain G = 4.0 motor gain G = 6.4 motor gain G = 8.0 motor gain G = 12.8 motor gain G = 16.0 motor gain G = 25.6 motor gain G = 32.0 disable comparator clock divider FUNCTION SAA7373 INITIAL(1) reset - - - - - - - reset - reset - - - reset - - reset - - - reset - - - reset - reset - reset - enable comparator clock divider; only if SELLPLL set HIGH motor f4 = 0.5 x n Hz motor f4 = 0.7 x n Hz motor f4 = 1.4 x n Hz motor f4 = 2.8 x n Hz motor f3 = 0.85 x n Hz motor f3 = 1.71 x n Hz motor f3 = 3.42 x n Hz motor power maximum 37% motor power maximum 50% motor power maximum 75% motor power maximum 100% MOTO1, MOTO2 pins 3-state motor PWM mode motor PDM mode motor CDV mode interrupt signal from servo at STATUS pin status bit from decoder status register at STATUS pin DAC data normal value DAC data inverted value left channel first at DAC (WCLK normal) right channel first at DAC (WCLK inverted) see Table 13 PLL loop filter equalization PLL 30 ns over-equalization PLL 15 ns over-equalization PLL 15 ns under-equalization PLL 30 ns under-equalization reset - - - - 1998 Jul 06 37 Philips Semiconductors Product specification Digital servo processor and Compact Disc decoder (CD7) REGISTER A (EBU output) ADDRESS 1010 DATA xx0x xx1x x0x0 x0x1 x1x0 x1x1 0xxx 1xxx B (speed control) 1011 x0xx x1xx 0xxx 1xxx xx00 xx10 xx11 C (versatile pins interface) 1100 xxx1 xxx0 xx0x 001x 011x D (versatile pins interface) 1101 0000 xx01 xx10 xx11 01xx 10xx 11xx E 1110 00xx 01xx xx0x xx1x xxx0 xxx1 FUNCTION EBU data before concealment EBU data after concealment and fade level II clock accuracy (<1000 ppm) level I clock accuracy (<50 ppm) level III clock accuracy (>1000 ppm) EBU off - output LOW flags in EBU off flags in EBU on SAA7373 INITIAL(1) - reset reset - - - reset - reset - reset - reset - - - reset - reset - - - - reset - - reset - reset reset - reset - 33.8688 MHz crystal present, or 8.4672 MHz crystal with SELPLL set HIGH 16.9344 MHz crystal present single-speed mode double-speed mode standby 1:'CD-STOP' mode standby 2:'CD-PAUSE' mode operating mode external off-track signal input at V1 internal off-track signal used (V1 may be read via STATUS) kill-L at KILL output, kill-R at V3 output V3 = 0; single KILL output V3 = 1; single KILL output 4-line motor (using V4 and V5) Q-to-W subcode at V4 V4 = 0 V4 = 1 de-emphasis signal at V5, no internal de-emphasis filter V5 = 0 V5 = 1 audio features disabled audio features enabled lock-to-disc mode disabled lock-to-disc mode enabled motor brakes to 12% motor brakes to 6% 1998 Jul 06 38 Philips Semiconductors Product specification Digital servo processor and Compact Disc decoder (CD7) REGISTER F (subcode interface) ADDRESS 1111 DATA x000 x100 0xxx 1xxx Note 1. The initial column shows the power-on reset state. Table 13 Loop filter bandwidth FUNCTION REGISTER ADDRESS DATA LOOP BANDWIDTH (Hz) 1640 x n 3279 x n 6560 x n 1640 x n 3279 x n 6560 x n 1640 x n 3279 x n 6560 x n 1640 x n 3279 x n 6560 x n INTERNAL BANDWIDTH (Hz) 525 x n 263 x n 131 x n 1050 x n 525 x n 263 x n 2101 x n 1050 x n 525 x n 4200 x n 2101 x n 1050 x n subcode interface off subcode interface on 4-wire subcode 3-wire subcode FUNCTION SAA7373 INITIAL(1) reset - reset - LOW-PASS BANDWIDTH (Hz) 8400 x n 16800 x n 33600 x n 8400 x n 16800 x n 33600 x n 8400 x n 16800 x n 33600 x n 8400 x n 16800 x n 33600 x n INITIAL(1) 8 (PLL loop filter bandwidth) 1000 0000 0001 0010 0100 0101 0110 1000 1001 1010 1100 1101 1110 - - - - - - - reset - - - - Note 1. The initial column shows the power-on reset state. 1998 Jul 06 39 Philips Semiconductors Product specification Digital servo processor and Compact Disc decoder (CD7) 7.15.4 SUMMARY OF SERVO COMMANDS SAA7373 A list of the servo commands are given in Table 14. It should be noted that these are not fully backwards compatible with DSIC2. Table 14 CD7 servo commands COMMANDS Write commands Write_focus_coefs1 Write_focus_coefs2 Write_focus_command Focus_gain_up Focus_gain_down Write_radial coefs Preset_Latch Radial_off Radial_init Short_jump Long_jump Steer_sledge Preset_init Write_decoder_reg(1) Write_parameter Read commands Read_Q_subcode(1)(2) Read_status Read_hilevel_status(3) Read_aux_status Notes 1. These commands only available when internal decoder interface is enabled. 2. 1998 Jul 06 40 Philips Semiconductors Product specification Digital servo processor and Compact Disc decoder (CD7) 7.15.5 SUMMARY OF SERVO COMMAND PARAMETERS SAA7373 Table 15 Servo command parameters PARAMETER foc_parm_1 foc_parm_2 foc_parm_3 foc_int foc_gain CA_drop ramp_offset ramp_height ramp_incr FE_start rad_parm_play rad_pole_noise rad_length_lead rad_int rad_gain rad_parm_jump vel_parm1 vel_parm2 speed_threshold hold_mult brake_dist_max sledge_long_brake sledge_Umax sledge_level sledge_parm_1 sledge_parm_2 RAM ADDRESS - - - 14H 15H 12H 16H 18H - 19H 28H 29H 1CH 1EH 2AH 27H 1FH 32H 48H 49H 21H 58H - - 36H 17H AFFECTS focus PID focus PID focus PID focus PID focus PID focus PID focus ramp focus ramp focus ramp focus ramp radial PID radial PID radial PID radial PID radial PID radial jump radial jump radial jump radial jump radial jump radial jump radial jump sledge sledge sledge sledge POR VALUE - - - - 70H - - - - - - - - - 70H - - - - 00H - 7FH - - - - end of focus lead defect detector enabling focus low-pass focus error normalising focus lead length minimum light level focus integrator crossover frequency focus PID loop gain sensitivity of drop-out detector asymmetry of focus ramp peak-to-peak value of ramp voltage slope of ramp voltage minimum value of focus error end of radial lead radial low-pass length of radial lead radial integrator crossover frequency radial loop gain filter during jump PI controller crossover frequencies jump pre-defined profile maximum speed in fastrad mode sledge bandwidth during jump maximum sledge distance allowed in fast actuator steered mode brake distance of sledge voltage on sledge during long jump voltage on sledge when steered sledge integrator crossover frequency sledge low-pass frequencies sledge gain sledge operation mode sledge_pulse1 sledge_pulse2 defect_parm shock_level playwatchtime jumpwatchtime 1998 Jul 06 46H 64H - - 54H 57H pulsed sledge pulsed sledge defect detector shock detector watchdog watchdog 41 - - - - - - pulse width pulse height defect detector setting shock detector operation radial on-track watchdog time radial jump watchdog time-out DETERMINES Philips Semiconductors Product specification Digital servo processor and Compact Disc decoder (CD7) PARAMETER radcontrol chip_init xtra_preset RAM ADDRESS 59H - 4AH AFFECTS watchdog set-up set-up POR VALUE - - 38H VRH level setting enable/disable decoder interface laser on/off DETERMINES SAA7373 enable/disable automatic radial off feature RA, FO and SL PDM modulating frequency microcontroller communication to decoder part cd6cmd interrupt_mask seq_control focus_start_time motor_start_time1 motor_start_time2 radial_init_time brake_time RadCmdByte osc_inc phase_shift level1 level2 agc_gain 4DH 53H 42H 5EH 5FH 60H 61H 62H 63H 68H 67H 69H 6AH 6CH decoder interface STATUS pin autosequencer autosequencer autosequencer autosequencer autosequencer autosequencer autosequencer focus/radial AGC focus/radial AGC focus/radial AGC focus/radial AGC focus/radial AGC - - - - - - - - - - - - - - decoder part commands enabled interrupts autosequencer control focus start time motor start 1 time motor start 2 time radial initialization time brake time radial command byte AGC control frequency of injected signal phase shift of injected signal amplitude of signal injected amplitude of signal injected focus/radial gain 1998 Jul 06 42 Philips Semiconductors Product specification Digital servo processor and Compact Disc decoder (CD7) 8 LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL VDD VI(max) VO VDDdiff IO IIK Tamb Tstg Ves PARAMETER supply voltage maximum Input voltage (any input) output voltage (any output) difference between VDDA and VDDD output current (continuous) DC input diode current (continuous) operating ambient temperature storage temperature electrostatic handling note 2 note 3 Notes 1. All VDD and VSS connections must be made externally to the same power supply. 2. Equivalent to discharging a 100 pF capacitor via a 1.5 k series resistor with a rise time of 15 ns. 3. Equivalent to discharging a 200 pF capacitor via a 2.5 H series inductor. 9 OPERATING CHARACTERISTICS VDD = 3.4 to 5.5 V; VSS = 0 V; Tamb = -10 to +70 C; unless otherwise specified. SYMBOL Supply VDD IDD supply voltage supply current VDD = 5 V; n = 1 mode 3.4 - 5.0 49 5.5 - PARAMETER CONDITIONS MIN. TYP. CONDITIONS note 1 MIN. -0.5 -0.5 -0.5 - - - -40 -55 -2000 -200 MAX. +6.5 VDD + 0.5 +6.5 0.25 20 20 +85 +125 +2000 +200 SAA7373 UNIT V V V V mA mA C C V V MAX. UNIT V mA Decoder analog front-end (VDDA = 5 V; VSSA = 0 V; Tamb = 25 C) COMPARATOR INPUTS: HFIN AND HFREF fclk Vth(sw) Vtpt VIref clock frequency switching voltage threshold HFIN input voltage level note 1 8 1.2 - - - - 1.0 70 VDD - 0.8 - - MHz V V REFERENCE GENERATOR: Iref reference voltage level (pin 18) 0.5VDD V 1998 Jul 06 43 Philips Semiconductors Product specification Digital servo processor and Compact Disc decoder (CD7) SYMBOL PARAMETER CONDITIONS MIN. TYP. SAA7373 MAX. UNIT Servo analog part (VDDA = 5 V; VSSA = 0 V; Tamb = 25 C) PINS D1 TO D4, R1, R2, VRH, VRL AND IrefT IrefT RIrefT VIrefT ID(max) IR(max) VRL VRH input reference current external resistor on pin 10 voltage on reference current input maximum input current for central diode input signal maximum input current for satellite diode input signal LOW level reference voltage HIGH level reference voltage output state 0; note 3 output state v; note 3 output state 31; note 3 (THD+N)/S total harmonic distortion plus at 0 dB; note 4 noise S/N PSRR Gtol Gv cs signal-to-noise ratio power supply ripple rejection note 5 at VDDA2 gain tolerance variation of gain between channels channel separation note 6 note 2 note 2 1.935 220 - 3.871 1.935 0 - -30% - - - - -12 - - - - 1.2 - - 0 0.5 0.5 x 10v/44.4 2.5 -50 55 45 0 - 60 5.45 620 - 10.9 5.45 0 - +30% - -45 - - +12 2 - A k V A A V V V V dB dB dB % % dB Digital inputs INPUTS: RESET, V1, V2, SELPLL (CMOS INPUT WITH PULL-UP RESISTOR AND HYSTERESIS) Vthr(sw) Vthf(sw) Vhys RI(pu) Cin tresL switching voltage threshold rising switching voltage threshold falling hysteresis voltage input pull-up resistance input capacitance reset pulse width (active LOW) RESET only Vi = 0 V - 0.2VDDD - - - 1 - - 0.33VDDD 50 - - 0.8VDDD - - - 10 - V V V k pF s INPUTS: SCL, RAB, SILD AND RCK (CMOS INPUT) VIL VIH ILI Cin LOW level input voltage HIGH level input voltage input leakage current input capacitance Vi = 0 - VDD -0.3 0.7VDD -10 - - - - - 0.3VDD VDD + 0.3 +10 10 V V A pF 1998 Jul 06 44 Philips Semiconductors Product specification Digital servo processor and Compact Disc decoder (CD7) SYMBOL Digital outputs OUTPUT: CL4 VOL VOH CL tr tf LOW level output voltage HIGH level output voltage load capacitance output rise time output fall time CL = 20 pF; 0.8 to (VDDD - 0.8) CL = 20 pF; (VDDD - 0.8) to 0.8 IOL = 1 mA IOH = -1 mA CL = 20 pF; 0.8 - (VDDD - 0.8) CL = 20 pF; (VDDD - 0.8) - 0.8 VDDD = 4.5 to 5.5 V; IOL = 10 mA VDDD = 3.4 to 5.5 V; IOL = 5 mA VOH HIGH level output voltage VDDD = 4.5 to 5.5 V; IOH = -10 mA VDDD = 3.4 to 5.5 V; IOH = -5 mA CL tr tf load capacitance output rise time output fall time CL = 20 pF; 0.8 - (VDDD - 0.8) CL = 20 pF; (VDDD - 0.8) - 0.8 IOL = 1 mA IOH = -1 mA 0 VDDD - 0.4 - - - - - - - - 0.4 PARAMETER CONDITIONS MIN. TYP. SAA7373 MAX. UNIT V V pF ns ns VDDD 25 20 20 OUTPUT: CL16 VOL VOH CL tr tf LOW level output voltage HIGH level output voltage load capacitance output rise time output fall time 0 VDDD - 0.4 - - - - - - - - 0.4 VDDD 50 15 15 V V pF ns ns OUTPUTS: V4 AND V5 VOL LOW level output voltage 0 0 VDDD - 1 VDDD - 1 - - - - - - - - - - 1.0 1.0 VDDD VDDD 50 10 10 V V V V pF ns ns Open-drain outputs OUTPUTS: CFLG, C2FAIL, STATUS, KILL, V3 AND LDON (OPEN-DRAIN OUTPUT WITH PROTECTION DIODE TO VDD) VOL IOL CL tf LOW level output voltage LOW level output current load capacitance output fall time CL = 20 pF; (VDDD - 0.8) - 0.8 IOL = 1 mA 0 - - - - - - - 0.4 2 25 30 V mA pF ns 1998 Jul 06 45 Philips Semiconductors Product specification Digital servo processor and Compact Disc decoder (CD7) SYMBOL 3-state outputs OUTPUTS: EF, CLK, WCLK, DATA AND CL11 VOL VOH CL tr tf IZO LOW level output voltage HIGH level output voltage load capacitance output rise time output fall time output 3-state leakage current CL = 20 pF; 0.8 - (VDD - 0.8) CL = 20 pF; (VDD - 0.8) - 0.8 Vi = 0 - VDD IOL = 1 mA IOH = -1 mA 0 VDD - 0.4 - - - -10 - - - - - - 0.4 VDD 50 15 15 +10 PARAMETER CONDITIONS MIN. TYP. SAA7373 MAX. UNIT V V pF ns ns A OUTPUT: CL11 tH output HIGH time (relative to Vo = 1.5 V clock period) 45 50 55 % OUTPUTS: RA, FO, SL, SBSY, SFSY AND SUB VOL VOH CL tr tf IZO VOL LOW level output voltage HIGH level output voltage load capacitance output rise time output fall time 3-state leakage current CL = 20 pF; 0.8 - (VDD - 0.8) CL = 20 pF; (VDD - 0.8) - 0.8 Vi = 0 - VDD VDD = 4.5 to 5.5 V; IOL = 10 mA VDD = 3.4 to 5.5 V; IOL = 5 mA VOH HIGH level output voltage VDD = 4.5 to 5.5 V; IOL = -10 mA VDD = 3.4 to 5.5 V; IOL = -5 mA CL tr tf IZO load capacitance output rise time output fall time 3-state leakage current CL = 20 pF; 0.8 - (VDD - 0.8) CL = 20 pF; (VDD - 0.8) - 0.8 Vi = 0 - VDD IOL = 1 mA IOH = -1 mA 0 VDD - 0.4 - - - -10 0 0 VDD - 1 VDD - 1 - - - -10 - - - - - - - - - - - - - - 0.4 VDD 25 20 20 +10 V V pF ns ns A V V V V pF ns ns A OUTPUTS: MOTO1, MOTO2 AND DOBM LOW level output voltage 1.0 1.0 VDD VDD 50 10 10 +10 1998 Jul 06 46 Philips Semiconductors Product specification Digital servo processor and Compact Disc decoder (CD7) SYMBOL PARAMETER CONDITIONS MIN. TYP. SAA7373 MAX. UNIT Digital input/output INPUT/OUTPUT: SDA [CMOS INPUT/OPEN-DRAIN I2C-BUS OUTPUT (WITH PROTECTION DIODE TO VDDD)] VIL VIH IZO Cin VOL Io CL tf LOW level input voltage HIGH level input voltage 3-state leakage current input capacitance LOW level output voltage output current load capacitance output fall time CL = 20 pF; (VDDD - 0.8) - 0.8 IOL = 2 mA Vi = 0 - VDDD -0.3 0.7VDDD -10 - 0 - - - - - - - - - - - 0.3VDDD VDDD + 0.3 +10 10 0.4 4 50 15 V V A pF V mA pF ns Crystal oscillator INPUT: CRIN (EXTERNAL CLOCK) VIL VIH ILI Cin fxtal gm GV Cfb Cout Notes 1. Highest clock frequency at which data slicer produces 1010 output in analog self-test mode. 2. VRL = 0 V, fsys = 4.2336 MHz. The maximum input current depends on the value of the external resistor connected to IrefT: a) For D1 to D4: Imax = 2.4 / RIrefT 2.4 / 220 k = 10.9 A b) For R1 and R2: Imax = 1.2 / RIrefT 1.2 / 220 k = 5.45 A 3. Internal reference source with 32 different output voltages. Selection is achieved during a calibration period or via the serial interface. The values given are for an unloaded VRH. 4. VRH = 2.5 V and VRL = 0 V, measuring bandwidth: 200 Hz to 20 kHz, fi(ADC) = 1 kHz. 5. fripple = 1 kHz, Vripple = 0.5 V (p-p). 6. Gain of the ADC is defined as GADC = fsys/Imax (counts/A); thus digital output = Ii x GADC where; a) Digital output = the number of pulses at the digital output in counts/s and Ii = the DC input current in A. b) The maximum input current depends on the system frequency (fsys = 4.2336 MHz) and on VRH - VRL. c) The gain tolerance is the deviation from the calculated gain regarding note 2. 7. It is recommended that the series resistance of the crystal or ceramic resonator is 60 . LOW level input voltage HIGH level input voltage input leakage current input capacitance -0.3 0.7VDD -10 - note 7 8 - GV = gm x RO - - - - - - - 8.4672 10 18 - - 0.3VDD VDD + 0.3 +10 10 V V A pF OUTPUT: CROUT; see Figs 3 and 4 crystal frequency mutual conductance at 100 kHz small signal voltage gain feedback capacitance output capacitance 35 - - 5 10 MHz mA/V V/V pF pF 1998 Jul 06 47 Philips Semiconductors Product specification Digital servo processor and Compact Disc decoder (CD7) 10 OPERATING CHARACTERISTICS (SUBCODE INTERFACE TIMING) VDD = 3.4 to 5.5 V; VSS = 0 V; Tamb = -10 to +70 C; unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. SAA7373 MAX. UNIT Subcode interface timing (single speed x n); see Fig.31; note 1 INPUT: RCK tH tL tr tf tdC tBcy tBW tFcy tFW tFH tFL tdPAC tdAC thD Note 1. The subcode timing is directly related to the overspeed factor `n' in normal operating mode. `n' is replaced by the disc speed factor `d', in the lock-to-disc mode. input clock HIGH time input clock LOW time input clock rise time input clock fall time delay time SFSY to RCK 2/n 2/n - - 10/n 4/n 4/n - - - 13.3/n - 136/n - - - - - - 6/n 6/n 80/n 80/n 20/n s s ns ns s ms s s s s s s s s OUTPUTS: SBSY, SFSY, SUB (CL = 20 pF) block cycle SBSY pulse width frame cycle SFSY pulse width (3-wire mode only) SFSY HIGH time SFSY LOW time delay time SFSY to SUB (P data) valid delay time RCK falling to SUB hold time RCK to SUB 12.0/n - 122/n - - - - - - 14.7/n 300/n 150/n 366/n 66/n 84/n 1/n 0 0.7/n 1998 Jul 06 48 Philips Semiconductors Product specification Digital servo processor and Compact Disc decoder (CD7) tW(SBSY) Tcy(block) SAA7373 handbook, full pagewidth SBSY tSFSYH SFSY (4-wire mode) tW(SFSY) SFSY (3-wire mode) tSFSYL tcy(frame) SFSY 0.8 V td(SFSY-RCK) tr tf VDD - 0.8 V RCK 0.8 V td(SFSY-SUB) th(RCK-SUB) td(RCK-SUB) VDD - 0.8 V SUB 0.8 V MBG414 Fig.31 Subcode interface timing diagram. 1998 Jul 06 49 Philips Semiconductors Product specification Digital servo processor and Compact Disc decoder (CD7) 11 OPERATING CHARACTERISTICS (I2S-BUS TIMING) VDD = 3.4 to 5.5 V; VSS = 0 V; Tamb = -10 to +70 C; unless otherwise specified SYMBOL PARAMETER CONDITIONS MIN. TYP. SAA7373 MAX. UNIT I2S-bus timing (single speed x n); see Fig.32; note 1 CLOCK OUTPUT: SCLK (CL = 20 pF) Tcy output clock period sample rate = fs sample rate = 2fs sample rate = 4fs tCH clock HIGH time sample rate = fs sample rate = 2fs sample rate = 4fs tCL clock LOW time sample rate = fs sample rate = 2fs sample rate = 4fs OUTPUTS: WCLK, DATA AND EF (CL = 20 pF) tsu set-up time sample rate = fs sample rate = 2fs sample rate = 4fs th hold time sample rate = fs sample rate = 2fs sample rate = 4fs Note 1. The I2S-bus timing is directly related to the overspeed factor `n' in the normal operating mode. In the lock-to-disc mode `n' is replaced by the disc speed factor `d'. 95/n 48/n 24/n 95/n 48/n 24/n - - - - - - - - - - - - ns ns ns ns ns ns - - - 166/n 83/n 42/n 166/n 83/n 42/n 472.4/n 236.2/n 118.1/n - - - - - - - - - - - - - - - ns ns ns ns ns ns ns ns ns clock period Tcy t CL t CH V SCLK 0.8 V th WCLK DATA EF t su V DD - 0.8 V 0.8 V MBG407 DD - 0.8 V Fig.32 I2S-bus timing diagram. 1998 Jul 06 50 Philips Semiconductors Product specification Digital servo processor and Compact Disc decoder (CD7) 12 OPERATING CHARACTERISTICS (MICROCONTROLLER INTERFACE TIMING) VDD = 3.4 to 5.5 V; VSS = 0 V; Tamb = -10 to +70 C; unless otherwise specified. NORMAL MODE SYMBOL PARAMETER CONDITIONS MIN. MAX. MIN. SAA7373 LOCK-TO-DISC MODE UNIT MAX. Microcontroller interface timing (4-wire bus mode; writing to registers 0 to F; reading Q-channel subcode and decoder status); see Figs 33 and 34; note 1 INPUTS SCL AND RAB tCL tCH tr tf tdRD tPD tdRZ input LOW time input HIGH time rise time fall time 480/n + 20 480/n + 20 - - - 720/n - 20 - - - 480/n 480/n 2400/n + 20 2400/n + 20 - - - 720/n + 20 - - - 480/n 480/n ns ns ns ns READ MODE (CL = 20 pF) delay time RAB to SDA valid propagation delay SCL to SDA delay time RAB to SDA high-impedance 50 960/n + 20 50 50 ns 4800/n + 20 ns 50 ns WRITE MODE ((CL = 20 pF) tsuD thD tsuCR tdWZ set-up time SDA to SCL hold time SCL to SDA set-up time SCL to RAB delay time SDA high-impedance to RAB note 2 20 - 720/n - 240/n + 20 0 - 960/n + 20 - - 20 - 720/n 1200/n + 20 0 - ns 4800/n + 20 ns - - ns ns Microcontroller interface timing (4-wire bus mode; servo commands); see Figs 35 and 36 INPUTS SCL AND SILD tL tH tr tf input LOW time input HIGH time rise time fall time 710 710 - - - - 240 240 710 710 - - - - 240 240 ns ns ns ns 1998 Jul 06 51 Philips Semiconductors Product specification Digital servo processor and Compact Disc decoder (CD7) NORMAL MODE SYMBOL PARAMETER CONDITIONS MIN. READ MODE (CL = 20 pF) tdLD tPD tdLZ tsCLR thCLR tsD thD tsCL thCL tdPLP tdWZ delay time SILD to SDA valid propagation delay SCL to SDA delay time SILD to SDA high-impedance set-up time SCL to SILD hold time SCL to SILD - - - 480 830 25 950 50 - - - - - - - - - - - 480 830 25 950 50 - - - - - - - - MAX. MIN. SAA7373 LOCK-TO-DISC MODE UNIT MAX. ns ns ns ns ns WRITE MODE (CL = 20 pF) set-up time SDA to SCL hold time SCL to SDA set-up time SCL to SILD hold time SILD to SCL delay between two SILD pulses delay time SDA high-impedance to SILD 0 950 480 120 70 0 0 950 480 120 70 0 ns ns ns ns s ns Notes 1. The 4-wire bus mode microprocessor interface timing for writing to registers 0 to F, and reading Q-channel subcode and decoder status, is a function of the overspeed factor `n'. In the lock-to-disc mode the maximum data rate is lower. 2. Negative set-up time means that the data may change after clock transition. 1998 Jul 06 52 Philips Semiconductors Product specification Digital servo processor and Compact Disc decoder (CD7) SAA7373 tr tf V DD - 0.8 V RAB tr tf tCH V DD - 0.8 V 0.8 V tCL tPD SDA (SAA7373) high-impedance V DD - 0.8 V 0.8 V MGR333 0.8 V SCL tdRD tdRZ Fig.33 4-wire bus microcontroller timing; read mode (Q-channel subcode and decoder status information). handbook, full pagewidth tr t suCR RAB t CH tf V DD - 0.8 V 0.8 V tf t CH tr VDD - 0.8 V t CL SCL 0.8 V t CL t suD V SDA (microcontroller) DD t hD t dWZ - 0.8 V high-impedance MBG405 0.8 V Fig.34 4-wire bus microcontroller timing; write mode (registers 0 to F). 1998 Jul 06 53 Philips Semiconductors Product specification Digital servo processor and Compact Disc decoder (CD7) SAA7373 handbook, full pagewidth VDD - 0.8 V SILD 0.8 V thCLR tsCLR VDD - 0.8 V SCL 0.8 V tdLD VDD - 0.8 V SDA (SAA7373) 0.8 V MGR334 tPD tdLZ Fig.35 4-wire bus microcontroller timing; read mode (servo commands). handbook, full pagewidth VDD - 0.8 V 0.8 V tsCL tH tL tdPLP VDD - 0.8 V SILD SCL 0.8 V thCL tsD thD VDD - 0.8 V SDA (microcontroller) 0.8 V tL tdWZ MBG416 Fig.36 4-wire bus microcontroller timing write mode (servo commands). 1998 Jul 06 54 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... 1998 Jul 06 +V LDON 7 2.2 VDDA D2 6 220 pF 100 k 220 pF 33 F 100 nF 1 2 3 4 5 6 7 8 9 10 270 k 11 12 13 100 nF (3) 13 APPLICATION INFORMATION Philips Semiconductors +V 2.2 VDDD Digital servo processor and Compact Disc decoder (CD7) +V 4.7 k microcontroller interface +V 4.7 k 33 F 100 nF 100 nF 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 LDON SILD RAB SCL C2FAIL VDDD3C STATUS RESET VSSD4 CFLG SDA CL4 n.c. V2 V1 VSSD3 VSSA1 VDDA1 D1 D2 D3 VRL D4 R1 R2 IrefT VRH VSSA2 SELPLL ISLICE HFIN SCLK 48 2.2 100 nF VDDD VDDD2(P) 47 WCLK DATA EF KILL V3 46 45 44 43 42 41 40 39 38 37 36 35 34 33 to DAC 3 D3 1 D4 D1 4 220 pF 220 pF 100 k 220 pF 220 pF D5 5 2 D6 SAA7373 V4 V5 VSSD2 SUB RCK SFSY SBSY MOTO2 VDDD1(P) TDA1300 (4) VDDA2 HFREF Iref TEST1 TEST2 TEST3 CL16 RA FO 1 nF CL11 1 k 47 pF 100 nF 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 (1) 22 nF (2) to power amplifiers VDD handbook, full pagewidth (1) The diagram is for 5 V application. For 3.4 V application an additional resistor of 150 k should be connected between pin 18 and ground. (2) For crystal oscillator circuit see Figs 3 and 4. (3) For single and double-speed applications a 1 k resistor should be used. For single-speed only applications a 2.2 k resistor should be used (4) The connections to TDA1300 are shown for single Foucault mechanisms. to DOBM transformer 2.2 DOBM CRIN SL VSSD1 RFE CROUT 55 to CD graphics MOTOR INTERFACE 22 k VDDA 14 15 9 16 VSSA3 MOTO1 Product specification 100 nF SAA7373 MGR335 Fig.37 Typical SAA7373 application diagram. Philips Semiconductors Product specification Digital servo processor and Compact Disc decoder (CD7) 14 PACKAGE OUTLINE QFP64: plastic quad flat package; 64 leads (lead length 1.6 mm); body 14 x 14 x 2.7 mm SAA7373 SOT393-1 c y X A 48 49 33 32 ZE e E HE wM pin 1 index 64 1 bp D HD wM ZD B vM B 16 vMA 17 bp Lp L detail X A A2 A1 (A 3) e 0 5 scale 10 mm DIMENSIONS (mm are the original dimensions) UNIT mm A max. 3.00 A1 0.25 0.10 A2 2.75 2.55 A3 0.25 bp 0.45 0.30 c 0.23 0.13 D (1) 14.1 13.9 E (1) 14.1 13.9 e 0.8 HD HE L Lp 1.03 0.73 v 0.16 w 0.16 y 0.10 Z D (1) Z E (1) 1.2 0.8 1.2 0.8 7 0o o 17.45 17.45 1.60 16.95 16.95 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT393-1 REFERENCES IEC JEDEC MS-022 EIAJ EUROPEAN PROJECTION ISSUE DATE 96-05-21 97-08-04 1998 Jul 06 56 Philips Semiconductors Product specification Digital servo processor and Compact Disc decoder (CD7) 15 SOLDERING 15.1 Introduction SAA7373 If wave soldering cannot be avoided, for QFP packages with a pitch (e) larger than 0.5 mm, the following conditions must be observed: * A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. * The footprint must be at an angle of 45 to the board direction and must incorporate solder thieves downstream and at the side corners. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Maximum permissible solder temperature is 260 C, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 C within 6 seconds. Typical dwell time is 4 seconds at 250 C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. 15.4 Repairing soldered joints There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "IC Package Databook" (order code 9398 652 90011). 15.2 Reflow soldering Reflow soldering techniques are suitable for all QFP packages. The choice of heating method may be influenced by larger plastic QFP packages (44 leads, or more). If infrared or vapour phase heating is used and the large packages are not absolutely dry (less than 0.1% moisture content by weight), vaporization of the small amount of moisture in them can cause cracking of the plastic body. For more information, refer to the Drypack chapter in our "Quality Reference Handbook" (order code 9397 750 00192). Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several methods exist for reflowing; for example, infrared/convection heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 50 and 300 seconds depending on heating method. Typical reflow peak temperatures range from 215 to 250 C. 15.3 Wave soldering Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron (less than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C. Wave soldering is not recommended for QFP packages. This is because of the likelihood of solder bridging due to closely-spaced leads and the possibility of incomplete solder penetration in multi-lead devices. CAUTION Wave soldering is NOT applicable for all QFP packages with a pitch (e) equal or less than 0.5 mm. 1998 Jul 06 57 Philips Semiconductors Product specification Digital servo processor and Compact Disc decoder (CD7) 16 DEFINITIONS Data sheet status Objective specification Preliminary specification Product specification Short-form specification Limiting values SAA7373 This data sheet contains target or goal specifications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications. The data in this specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. 17 LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. 18 PURCHASE OF PHILIPS I2C COMPONENTS Purchase of Philips I2C components conveys a license under the Philips' I2C patent to use the components in the I2C system provided the system conforms to the I2C specification defined by Philips. This specification can be ordered using the code 9398 393 40011. 1998 Jul 06 58 Philips Semiconductors Product specification Digital servo processor and Compact Disc decoder (CD7) NOTES SAA7373 1998 Jul 06 59 Philips Semiconductors - a worldwide company Argentina: see South America Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113, Tel. +61 2 9805 4455, Fax. +61 2 9805 4466 Austria: Computerstr. 6, A-1101 WIEN, P.O. Box 213, Tel. +43 160 1010, Fax. +43 160 101 1210 Belarus: Hotel Minsk Business Center, Bld. 3, r. 1211, Volodarski Str. 6, 220050 MINSK, Tel. +375 172 200 733, Fax. +375 172 200 773 Belgium: see The Netherlands Brazil: see South America Bulgaria: Philips Bulgaria Ltd., Energoproject, 15th floor, 51 James Bourchier Blvd., 1407 SOFIA, Tel. +359 2 689 211, Fax. +359 2 689 102 Canada: PHILIPS SEMICONDUCTORS/COMPONENTS, Tel. +1 800 234 7381 China/Hong Kong: 501 Hong Kong Industrial Technology Centre, 72 Tat Chee Avenue, Kowloon Tong, HONG KONG, Tel. +852 2319 7888, Fax. +852 2319 7700 Colombia: see South America Czech Republic: see Austria Denmark: Prags Boulevard 80, PB 1919, DK-2300 COPENHAGEN S, Tel. +45 32 88 2636, Fax. +45 31 57 0044 Finland: Sinikalliontie 3, FIN-02630 ESPOO, Tel. +358 9 615800, Fax. +358 9 61580920 France: 51 Rue Carnot, BP317, 92156 SURESNES Cedex, Tel. +33 1 40 99 6161, Fax. +33 1 40 99 6427 Germany: Hammerbrookstrae 69, D-20097 HAMBURG, Tel. +49 40 23 53 60, Fax. +49 40 23 536 300 Greece: No. 15, 25th March Street, GR 17778 TAVROS/ATHENS, Tel. +30 1 4894 339/239, Fax. +30 1 4814 240 Hungary: see Austria India: Philips INDIA Ltd, Band Box Building, 2nd floor, 254-D, Dr. Annie Besant Road, Worli, MUMBAI 400 025, Tel. +91 22 493 8541, Fax. +91 22 493 0966 Indonesia: PT Philips Development Corporation, Semiconductors Division, Gedung Philips, Jl. Buncit Raya Kav.99-100, JAKARTA 12510, Tel. +62 21 794 0040 ext. 2501, Fax. +62 21 794 0080 Ireland: Newstead, Clonskeagh, DUBLIN 14, Tel. +353 1 7640 000, Fax. +353 1 7640 200 Israel: RAPAC Electronics, 7 Kehilat Saloniki St, PO Box 18053, TEL AVIV 61180, Tel. +972 3 645 0444, Fax. +972 3 649 1007 Italy: PHILIPS SEMICONDUCTORS, Piazza IV Novembre 3, 20124 MILANO, Tel. +39 2 6752 2531, Fax. +39 2 6752 2557 Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku, TOKYO 108-8507, Tel. +81 3 3740 5130, Fax. +81 3 3740 5077 Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL, Tel. +82 2 709 1412, Fax. +82 2 709 1415 Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR, Tel. +60 3 750 5214, Fax. +60 3 757 4880 Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905, Tel. +9-5 800 234 7381 Middle East: see Italy Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB, Tel. +31 40 27 82785, Fax. +31 40 27 88399 New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND, Tel. +64 9 849 4160, Fax. +64 9 849 7811 Norway: Box 1, Manglerud 0612, OSLO, Tel. +47 22 74 8000, Fax. +47 22 74 8341 Pakistan: see Singapore Philippines: Philips Semiconductors Philippines Inc., 106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI, Metro MANILA, Tel. +63 2 816 6380, Fax. +63 2 817 3474 Poland: Ul. Lukiska 10, PL 04-123 WARSZAWA, Tel. +48 22 612 2831, Fax. +48 22 612 2327 Portugal: see Spain Romania: see Italy Russia: Philips Russia, Ul. Usatcheva 35A, 119048 MOSCOW, Tel. +7 095 755 6918, Fax. +7 095 755 6919 Singapore: Lorong 1, Toa Payoh, SINGAPORE 319762, Tel. +65 350 2538, Fax. +65 251 6500 Slovakia: see Austria Slovenia: see Italy South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale, 2092 JOHANNESBURG, P.O. Box 7430 Johannesburg 2000, Tel. +27 11 470 5911, Fax. +27 11 470 5494 South America: Al. Vicente Pinzon, 173, 6th floor, 04547-130 SAO PAULO, SP, Brazil, Tel. +55 11 821 2333, Fax. +55 11 821 2382 Spain: Balmes 22, 08007 BARCELONA, Tel. +34 93 301 6312, Fax. +34 93 301 4107 Sweden: Kottbygatan 7, Akalla, S-16485 STOCKHOLM, Tel. +46 8 5985 2000, Fax. +46 8 5985 2745 Switzerland: Allmendstrasse 140, CH-8027 ZURICH, Tel. +41 1 488 2741 Fax. +41 1 488 3263 Taiwan: Philips Semiconductors, 6F, No. 96, Chien Kuo N. Rd., Sec. 1, TAIPEI, Taiwan Tel. +886 2 2134 2865, Fax. +886 2 2134 2874 Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd., 209/2 Sanpavuth-Bangna Road Prakanong, BANGKOK 10260, Tel. +66 2 745 4090, Fax. +66 2 398 0793 Turkey: Talatpasa Cad. No. 5, 80640 GULTEPE/ISTANBUL, Tel. +90 212 279 2770, Fax. +90 212 282 6707 Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7, 252042 KIEV, Tel. +380 44 264 2776, Fax. +380 44 268 0461 United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes, MIDDLESEX UB3 5BX, Tel. +44 181 730 5000, Fax. +44 181 754 8421 United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409, Tel. +1 800 234 7381 Uruguay: see South America Vietnam: see Singapore Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD, Tel. +381 11 625 344, Fax.+381 11 635 777 Internet: http://www.semiconductors.philips.com For all other countries apply to: Philips Semiconductors, International Marketing & Sales Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 (c) Philips Electronics N.V. 1998 SCA60 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands 545102/00/01/pp60 Date of release: 1998 Jul 06 Document order number: 9397 750 04002 |
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